ZHCSPO2 September 2023 ADC32RF52
PRODUCTION DATA
The device includes a 20-bit output resolution mode which can be used for high order decimation (e.g. 64x, 128x) to avoid SNR degradation due to quantization noise limitation. In this mode the output data is transmitted at 2x the output rate. The 20-bit sample from the DDC gets expanded to 32-bit by adding 12x 0s, and occupies 2 consecutive 16-bit samples. This doubles the number of octets 'F' and the proper LMFS mode and JESD PLL settings have to be selected.
So for example a single band complex decimation would go from LMFS = 2441 (16-bit output mode) to LMFS = 2481 (20-bit output mode) as illustrated in Table 7-18.
| LMFS = 2441 | LMFS = 2481 | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| xI0[15:8] | xI0[7:0] | xQ0[15:8] | xQ0[7:0] | xI0[31:24] | xI0[23:16] | xI0[15:8] | xI0[7:0] | xQ0[31:24] | xQ0[23:16] | xQ0[15:8] | xQ0[7:0] | |||
| 20-bit sample I | 0000 0000000 | 20-bit sample Q | 0000 0000000 | |||||||||||
The 20-bit output mode is enabled by setting D7 in 0x2C (DIGITAL page) and selecting viable decimation and LMFS mode.