產(chǎn)品詳情

DSP type 0 Operating system Linux Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 85
DSP type 0 Operating system Linux Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZCE) 338 169 mm2 13 x 13
  • Highlights
    • High-Performance Digital Media System-on-Chip (DMSoC)
    • Up to 300-MHz ARM926EJ-S Clock Rate
    • Two Video Image Co-processors (HDVICP, MJCP) Engines
    • Supports a Range of Encode, Decode, and Video Quality Operations
    • Video Processing Subsystem
      • HW Face Detect Engine
      • Resize Engine from 1/16x to 8x
      • 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
      • 4:2:2 (8-/16-bit) Interface
      • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 DACs for HD Analog Video Output
      • Hardware On-Screen Display (OSD)
    • Capable of 720p 30fps H.264 video processing
      Note: 216-MHz is only capable of D1 processing
    • Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan
    • 8 Different Boot Modes and Configurable Power-Saving Modes
    • Pin-to-pin and software compatible with DM368
    • Extended temperature (-40°C - 85°C) available for 300-Mhz device
    • 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core
    • 338-Pin Ball Grid Array at 65nm Process Technology
  • High-Performance Digital Media System-on-Chip (DMSoC)
    • 216-, 270-, 300-MHz ARM926EJ-S Clock Rate
    • Fully Software-Compatible With ARM9?
  • ARM926EJ-S? Core
    • Support for 32-Bit and 16-Bit (Thumb? Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM? Jazelle? Technology
    • EmbeddedICE-RT Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 16K-Byte ROM
    • Little Endian
  • Two Video Image Co-processors (HDVICP, MJCP) Engines
    • Support a Range of Encode and Decode Operations
    • H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
  • Video Processing Subsystem
    • Front End Provides:
      • HW Face Detect Engine
      • Hardware IPIPE for Real-Time Image Processing
        • Resize Engine
          • Resize Images From 1/16× to 8×
          • Separate Horizontal/Vertical Control
          • Two Simultaneous Output Paths
      • IPIPE Interface (IPIPEIF)
      • Image Sensor Interface (ISIF) and CMOS Imager Interface
      • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
      • Glueless Interface to Common Video Decoders
      • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit Module
      • Histogram Module
      • Lens distortion correction module (LDC)
      • Hardware 3A statistics collection module (H3A)
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 DACs for HD Analog Video Output
      • LCD Controller
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  • Analog-to-Digital Convertor (ADC)
  • Power Management and Real Time Clock Subsystem (PRTCSS)
    • Real Time Clock
  • 16-Bit Host-Port Interface (HPI)
  • 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Key Scan
  • Voice Codec
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • 16 MB NOR Flash, SRAM
        • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia/xD
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 High-Speed Device
    • USB 2.0 High-Speed Host (mini-host, supporting one external device)
    • USB On The Go (HS-USB OTG)
  • Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One fast UART with RTS and CTS Flow Control)
  • Five Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit (I2C) Bus?
  • One Multi-Channel Buffered Serial Port (McBSP)
    • I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
    • Direct Interface to T1/E1 Framers
    • Time Division Multiplexed Mode (TDM)
    • 128 Channel Mode
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • Boot Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
    • AEMIF (NOR and OneNAND)
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG?) Boundary-Scan-Compatible
    • ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 65nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal
  • Community Reesources

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Windows is a trademark of Microsoft.

All other trademarks are the property of their respective owners.

  • Highlights
    • High-Performance Digital Media System-on-Chip (DMSoC)
    • Up to 300-MHz ARM926EJ-S Clock Rate
    • Two Video Image Co-processors (HDVICP, MJCP) Engines
    • Supports a Range of Encode, Decode, and Video Quality Operations
    • Video Processing Subsystem
      • HW Face Detect Engine
      • Resize Engine from 1/16x to 8x
      • 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
      • 4:2:2 (8-/16-bit) Interface
      • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 DACs for HD Analog Video Output
      • Hardware On-Screen Display (OSD)
    • Capable of 720p 30fps H.264 video processing
      Note: 216-MHz is only capable of D1 processing
    • Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan
    • 8 Different Boot Modes and Configurable Power-Saving Modes
    • Pin-to-pin and software compatible with DM368
    • Extended temperature (-40°C - 85°C) available for 300-Mhz device
    • 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core
    • 338-Pin Ball Grid Array at 65nm Process Technology
  • High-Performance Digital Media System-on-Chip (DMSoC)
    • 216-, 270-, 300-MHz ARM926EJ-S Clock Rate
    • Fully Software-Compatible With ARM9?
  • ARM926EJ-S? Core
    • Support for 32-Bit and 16-Bit (Thumb? Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM? Jazelle? Technology
    • EmbeddedICE-RT Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 16K-Byte ROM
    • Little Endian
  • Two Video Image Co-processors (HDVICP, MJCP) Engines
    • Support a Range of Encode and Decode Operations
    • H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
  • Video Processing Subsystem
    • Front End Provides:
      • HW Face Detect Engine
      • Hardware IPIPE for Real-Time Image Processing
        • Resize Engine
          • Resize Images From 1/16× to 8×
          • Separate Horizontal/Vertical Control
          • Two Simultaneous Output Paths
      • IPIPE Interface (IPIPEIF)
      • Image Sensor Interface (ISIF) and CMOS Imager Interface
      • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
      • Glueless Interface to Common Video Decoders
      • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit Module
      • Histogram Module
      • Lens distortion correction module (LDC)
      • Hardware 3A statistics collection module (H3A)
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 DACs for HD Analog Video Output
      • LCD Controller
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  • Analog-to-Digital Convertor (ADC)
  • Power Management and Real Time Clock Subsystem (PRTCSS)
    • Real Time Clock
  • 16-Bit Host-Port Interface (HPI)
  • 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Key Scan
  • Voice Codec
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • 16 MB NOR Flash, SRAM
        • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia/xD
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 High-Speed Device
    • USB 2.0 High-Speed Host (mini-host, supporting one external device)
    • USB On The Go (HS-USB OTG)
  • Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One fast UART with RTS and CTS Flow Control)
  • Five Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit (I2C) Bus?
  • One Multi-Channel Buffered Serial Port (McBSP)
    • I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
    • Direct Interface to T1/E1 Framers
    • Time Division Multiplexed Mode (TDM)
    • 128 Channel Mode
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • Boot Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
    • AEMIF (NOR and OneNAND)
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG?) Boundary-Scan-Compatible
    • ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 65nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal
  • Community Reesources

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Windows is a trademark of Microsoft.

All other trademarks are the property of their respective owners.

Developers can now deliver pixel-perfect images at up to 720p H.264 at 30fps in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). With multi-format HD video, the DM365 also features a suite of peripherals saving developers on system costs.

This ARM9-based DM365 device offers speeds up to 300 MHz and supports production-qualified H.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can ensure interoperability as well as product scalability by taking advantage of the full suite of codecs supported on the DM365.

Along with multi-format HD video, the DM365 enables seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design.

Developers can now deliver pixel-perfect images at up to 720p H.264 at 30fps in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). With multi-format HD video, the DM365 also features a suite of peripherals saving developers on system costs.

This ARM9-based DM365 device offers speeds up to 300 MHz and supports production-qualified H.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can ensure interoperability as well as product scalability by taking advantage of the full suite of codecs supported on the DM365.

Along with multi-format HD video, the DM365 enables seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 TMS320DM365 Digital Media System-on-Chip 數(shù)據(jù)表 (Rev. E) 2011年 7月 1日
* 勘誤表 TMS320DM365 Digital Media System-on-Chip Silicon Errata (Silicon Revs 1.1 & 1.2) (Rev. E) 2011年 7月 11日
應(yīng)用手冊 高速接口布局指南 (Rev. J) PDF | HTML 英語版 (Rev.J) PDF | HTML 2023年 3月 23日
用戶指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
用戶指南 TMS320DM36x DaVinci? Video Processing Front End (VPFE) User's Guide (Rev. C) 2016年 6月 30日
應(yīng)用手冊 Powering the TMS320DM365 using the TPS650061 2012年 5月 10日
用戶指南 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem User's Guide (Rev. B) 2011年 8月 3日
應(yīng)用手冊 Migrating From TMS320DM35x to TMS320DM36x Devices (Rev. A) 2011年 6月 2日
用戶指南 TMS320DM36x DMSoC General-Purpose Input/Output User's Guide (Rev. C) 2011年 1月 19日
用戶指南 TMS320DM36x DMSoC Ethernet Media Access Controller (EMAC) User's Guide (Rev. B) 2010年 12月 23日
用戶指南 TMS320DM36x DMSoC Video Processing Front End User's Guide (Rev. C) 2010年 11月 12日
用戶指南 TMS320DM36x DMSoC Video Processing Back End User's Guide (Rev. C) 2010年 8月 26日
用戶指南 TMS320DM36x DMSoC Voice Codec User's Guide (Rev. B) 2010年 7月 30日
用戶指南 TMS320DM36x DMSoC Face Detection User's Guide (Rev. A) 2010年 7月 21日
應(yīng)用手冊 Application Parameter Settings for TMS320DM365 H.264 Encoder 2010年 4月 29日
用戶指南 TMS320DM36x DMSoC Asynchronous External Memory Interface User's Guide (Rev. C) 2010年 4月 23日
用戶指南 TMS320DM36x DMSoC Multimedia Card/Secure Digital Card Controller User's Guide (Rev. B) 2010年 4月 23日
應(yīng)用手冊 Migrating from TMS320DM365 to TMS320DM368 2010年 4月 11日
更多文獻(xiàn)資料 TMS320DM3x DaVinci Video Processors 2010年 4月 11日
用戶指南 TMS320DM36x DMSoC Key Scan User's Guide (Rev. A) 2010年 3月 1日
用戶指南 TMS320DM36x DMSoC Serial Peripheral Interface User's Guide (Rev. B) 2010年 3月 1日
應(yīng)用手冊 Smart Codec Features in TMS320DM365 2009年 12月 9日
應(yīng)用手冊 TMS320DM365 Preview of Codec Porting on Linux 2009年 12月 4日
應(yīng)用手冊 Understanding H.264 Decoder Buffer Mechanism for TMS320DM365 2009年 12月 4日
應(yīng)用手冊 High-Efficiency Power Solution Using DC/DC Converter for the DM365 (Rev. A) 2009年 9月 11日
應(yīng)用手冊 Simple Power Solution Using LDOs for the DM365 (Rev. A) 2009年 9月 11日
應(yīng)用手冊 High Integration, High Efficiency Power Solution using DCDC Converters for DM365 (Rev. A) 2009年 9月 11日
應(yīng)用手冊 TMS320DM36x Power Consumption Summary 2009年 9月 10日
用戶指南 TMS320DM36x DMSoC Universal Host Port Interface User's Guide (Rev. A) 2009年 8月 9日
用戶指南 TMS320DM36x DMSoC ARM Subsystem Reference Guide (Rev. A) 2009年 8月 7日
用戶指南 TMS320DM36x DMSoC Inter-Integrated Circuit User's Guide (Rev. A) 2009年 8月 7日
用戶指南 TMS320DM36x DMSoC Multichannel Buffered Serial Port User's Guide (Rev. A) 2009年 8月 7日
用戶指南 TMS320DM36x DMSoC Universal Serial Bus User's Guide (Rev. A) 2009年 8月 7日
應(yīng)用手冊 High Integration, High Efficiency Power Solution using DCDC Converters for DM365 2009年 8月 4日
應(yīng)用手冊 High-Vin, High-Efficiency Power Solution Using DC/DC Converter for the DM365 2009年 8月 4日
應(yīng)用手冊 Simple Power Solution Using LDOs for the DM365 2009年 8月 4日
應(yīng)用手冊 TMS320DM36x SoC Architecture and Throughput 2009年 7月 29日
應(yīng)用手冊 LSP 2.10 DaVinci Linux Drivers (Rev. A) 2009年 7月 8日
更多文獻(xiàn)資料 Complimentary Analog Devices for DM365 Digital Media Processor 2009年 3月 3日
用戶指南 TMS320DM36x DMSoC Analog to Digital Converter User's Guide 2009年 3月 3日
用戶指南 TMS320DM36x DMSoC DDR2/mDDR Memory Controller User's Guide 2009年 3月 3日
用戶指南 TMS320DM36x DMSoC Enhanced Direct Memory Access Controller User's Guide 2009年 3月 3日
用戶指南 TMS320DM36x DMSoC Pulse-Width Modulator User's Guide 2009年 3月 3日
用戶指南 TMS320DM36x DMSoC Real Time Out User's Guide 2009年 3月 3日
用戶指南 TMS320DM36x DMSoC Timer/Watchdog Timer User's Guide 2009年 3月 3日
用戶指南 TMS320DM36x DMSoC Universal Asynchronous Receiver/Transmitter User's Guide 2009年 3月 3日
應(yīng)用手冊 Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日

設(shè)計和開發(fā)

如需其他信息或資源，請點擊以下任一標(biāo)題進(jìn)入詳情頁面查看（如有）。

評估板

TMDXEVM368 — TMS320DM36x 評估模塊

借助 TMS320DM36x 數(shù)字視頻評估模塊 (DVEVM)，開發(fā)人員可直接評估 TI 的數(shù)字媒體 (DMx) 處理器，并開始構(gòu)建數(shù)字視頻應(yīng)用，如 IP 安防攝像頭、運(yùn)動相機(jī)、無人機(jī)、可穿戴器件、數(shù)字標(biāo)牌、可視門鈴及其他數(shù)字視頻產(chǎn)品

TMS320DM36x DVEVM 使開發(fā)人員能夠編寫適用于 ARM 的生產(chǎn)就緒型應(yīng)用代碼，并使用 DMx API 訪問 HDVICP 協(xié)處理器核心，從而直接開始開發(fā) TMS320DM368 和 TMS320DM365 數(shù)字媒體處理器的應(yīng)用。

用戶指南: PDF
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調(diào)試探針

TMDSEMU200-U — XDS200 USB 調(diào)試探針

XDS200 是用于調(diào)試 TI 嵌入式器件的調(diào)試探針（仿真器）。? 與低成本的 XDS110 和高性能的 XDS560v2 相比，XDS200 在低成本和高性能之間實現(xiàn)了平衡。? 它在單個倉體中支持廣泛的標(biāo)準(zhǔn)（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 調(diào)試探針在所有具有嵌入式跟蹤緩沖器 (ETB) 的 Arm? 和 DSP 處理器中均支持內(nèi)核和系統(tǒng)跟蹤。??對于引腳上的內(nèi)核跟蹤，則需要使用?XDS560v2 PRO TRACE。

XDS200 通過 TI 20 引腳連接器（帶有適用于 TI 14 引腳、Arm Cortex? 10 引腳和 Arm 20 (...)

TI.com 上無現(xiàn)貨
調(diào)試探針

TMDSEMU560V2STM-U — XDS560? 軟件 v2 系統(tǒng)跟蹤 USB 調(diào)試探針

XDS560v2 是 XDS560™ 系列調(diào)試探針中性能非常出色的產(chǎn)品，同時支持傳統(tǒng) JTAG 標(biāo)準(zhǔn) (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，它不支持串行線調(diào)試 (SWD)。

所有 XDS 調(diào)試探針在所有具有嵌入式跟蹤緩沖器 (ETB) 的 ARM 和 DSP 處理器中均支持內(nèi)核和系統(tǒng)跟蹤。對于引腳上的跟蹤，需要 XDS560v2 PRO TRACE。

XDS560v2 通過 MIPI HSPT 60 引腳連接器（帶有多個用于 TI 14 引腳、TI 20 引腳和 ARM 20 引腳的適配器）連接到目標(biāo)板，并通過 USB2.0 高速 (480Mbps) (...)

TI.com 上無現(xiàn)貨
調(diào)試探針

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系統(tǒng)跟蹤 USB 和以太網(wǎng)

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 處理器調(diào)試探針（仿真器）的第一種型號。XDS560v2 是 XDS 系列調(diào)試探針中性能最高的一款，同時支持傳統(tǒng) JTAG 標(biāo)準(zhǔn) (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存儲器緩沖區(qū)中加入了系統(tǒng)引腳跟蹤。這種外部存儲器緩沖區(qū)適用于指定的 TI 器件，通過捕獲相關(guān)器件級信息，獲得準(zhǔn)確的總線性能活動和吞吐量，并對內(nèi)核和外設(shè)進(jìn)行電源管理。此外，對于帶有嵌入式緩沖跟蹤器 (ETB) 的所有 ARM 和 DSP 處理器，所有 XDS (...)

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調(diào)試探針

LB-3P-TRACE32-DSP — 適用于數(shù)字信號處理器 (DSP) 的 Lauterbach TRACE32 調(diào)試和跟蹤系統(tǒng)

Lauterbach‘s TRACE32? tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

來源：Lauterbach GmbH
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軟件開發(fā)套件 (SDK)

LINUXDVSDK-DM36X — 用于 DM365、DM368 數(shù)字媒體處理器的 Linux 數(shù)字視頻軟件開發(fā)套件 (DVSDK)

Linux? 數(shù)字視頻軟件開發(fā)套件 (DVSDK) 使 DaVinci? 系統(tǒng)集成商能夠快速開發(fā)基于 Linux 的多媒體應(yīng)用，它們可以輕松植入達(dá)芬奇平臺的不同器件中。每個 DVSDK 都包含一套預(yù)先測試的操作系統(tǒng)、應(yīng)用程序框架和具有示例程序的編解碼器庫，這些程序演示了從外設(shè)流入和流出的實時音頻和視頻數(shù)據(jù)的解碼和編碼。針對具有 DSP 內(nèi)核的達(dá)芬奇器件，DVSDK 提供了完整的框架，便于開發(fā)人員輕松利用 DSP 加速編解碼器，而無需對 DSP 進(jìn)行編程。DVSDK 完全免費，無需任何運(yùn)行版稅。

此版本 Linux DVSDK 4 版的正式 (GA) (...)

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軟件編解碼器

DM365CODECS — DM36x (DM365、DM368) 編解碼器 - 軟件和文檔

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的產(chǎn)品和硬件

支持的產(chǎn)品和硬件

產(chǎn)品
數(shù)字信號處理器 (DSP)
TMS320DM365 — DaVinci 數(shù)字媒體處理器 TMS320DM368 — DaVinci 數(shù)字媒體處理器
下載選項
仿真模型

DM365 ZCE BSDL Model

SPRM363.ZIP (9 KB) - BSDL Model
下載
仿真模型

DM365 ZCE IBIS Model (Rev. C)

SPRM354C.ZIP (502 KB) - IBIS Model
下載
封裝 引腳 CAD 符號、封裝和 3D 模型
NFBGA (ZCE) 338 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓(xùn)

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