SN74AUP2G79
- Available in the Texas Instruments NanoStar Package
- Low Static-Power Consumption
(ICC = 0.9 μA Maximum) - Low Dynamic-Power Consumption
(Cpd = 3 pF Typ at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
NanoStar is a trademark of Texas Instruments.
The AUP family is TIs premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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技術文檔
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | SN74AUP2G79 Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop 數(shù)據(jù)表 (Rev. C) | 2012年 7月 30日 | |||
| 應用簡報 | 了解施密特觸發(fā)器 (Rev. B) | PDF | HTML | 英語版 (Rev.B) | PDF | HTML | 2025年 5月 5日 | |
| 應用手冊 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |||
| 選擇指南 | Little Logic Guide 2018 (Rev. G) | 2018年 7月 6日 | ||||
| 選擇指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
| 應用手冊 | How to Select Little Logic (Rev. A) | 2016年 7月 26日 | ||||
| 選擇指南 | 邏輯器件指南 2014 (Rev. AA) | 最新英語版本 (Rev.AC) | PDF | HTML | 2014年 11月 17日 | ||
| 選擇指南 | 小尺寸邏輯器件指南 (Rev. E) | 最新英語版本 (Rev.G) | 2012年 7月 16日 | |||
| 應用手冊 | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
| 選擇指南 | Logic Guide (Rev. AC) | PDF | HTML | 1994年 6月 1日 |
設計和開發(fā)
如需其他信息或資源,請點擊以下任一標題進入詳情頁面查看(如有)。
5-8-LOGIC-EVM — 支持 5 至 8 引腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模塊
| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| UQFN (RSE) | 8 | Ultra Librarian |
| VSSOP (DCU) | 8 | Ultra Librarian |
| X2SON (DQE) | 8 | Ultra Librarian |
訂購和質量
- RoHS
- REACH
- 器件標識
- 引腳鍍層/焊球材料
- MSL 等級/回流焊峰值溫度
- MTBF/時基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測
- 制造廠地點
- 封裝廠地點