SN74AUP1T00

正在供貨

低功耗、1.8/2.5/3.3V 輸入、3.3V CMOS 輸出、單通道 2 輸入正與非門

產(chǎn)品詳情

Technology family AUP1T Number of channels 1 Vout (min) (V) 2.3 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) 4 Supply current (max) (μA) 0.9 Features Over-voltage tolerant inputs, Partial power down (Ioff), Single supply, Voltage translation Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85
Technology family AUP1T Number of channels 1 Vout (min) (V) 2.3 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) 4 Supply current (max) (μA) 0.9 Features Over-voltage tolerant inputs, Partial power down (Ioff), Single supply, Voltage translation Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 5 4.2 mm2 2 x 2.1
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and Provide Better
    Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 μA
  • Very Low Dynamic Power Consumption:
    0.9 μA
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)
    2 × 2.1 × 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and Provide Better
    Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 μA
  • Very Low Dynamic Power Consumption:
    0.9 μA
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)
    2 × 2.1 × 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

The SN74AUP1T00 performs the Boolean function Y = A • B or Y = A + B with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T00 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

The SN74AUP1T00 performs the Boolean function Y = A • B or Y = A + B with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T00 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
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* 數(shù)據(jù)表 Low Power, 1.8/2.5/3.3-V In, 3.3-V CMOS Out, Single 2-Input Positive-NAND Gate 數(shù)據(jù)表 2010年 4月 16日
應(yīng)用簡(jiǎn)報(bào) 了解施密特觸發(fā)器 (Rev. B) PDF | HTML 英語(yǔ)版 (Rev.B) PDF | HTML 2025年 5月 5日
選擇指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日

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靈活的 EVM 設(shè)計(jì)用于支持具有 5 至 8 引腳數(shù)且采用 DCK、DCT、DCU、DRL 或 DBV 封裝的任何器件。
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參考設(shè)計(jì)

TIDA-010050 — 適用于 AMR 的超低功耗水流測(cè)量參考設(shè)計(jì)

此參考設(shè)計(jì)經(jīng)過(guò)全面測(cè)試，展示了一個(gè)通過(guò)機(jī)械流量計(jì)對(duì)水流進(jìn)行電子測(cè)量的低功耗解決方案，并提供了用于水流測(cè)量和無(wú)線通信的單芯片平臺(tái)。該設(shè)計(jì)非常適用于水表自動(dòng)抄表 (AMR) 模塊，該模塊可在現(xiàn)有機(jī)械流量計(jì)上添加無(wú)線通信功能。射頻子系統(tǒng)支持無(wú)線 M-Bus 等標(biāo)準(zhǔn)協(xié)議或低于 1GHz ISM 頻帶的專有協(xié)議。此參考設(shè)計(jì)可提供遠(yuǎn)距離精確讀取機(jī)械旋轉(zhuǎn)量的能力，并提供更高的可靠性。超低的功耗可降低對(duì)電池的要求并延長(zhǎng)產(chǎn)品壽命。
設(shè)計(jì)指南: PDF
原理圖: PDF
封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
SOT-SC70 (DCK) 5 Ultra Librarian

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  • REACH
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  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
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