主頁 接口 LVDS、M-LVDS 和 PECL IC

SN65LVDS33-EP

正在供貨

增強(qiáng)型產(chǎn)品高速差動接收器

產(chǎn)品詳情

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL Output signal LVTTL Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL Output signal LVTTL Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOIC (D) 16 59.4 mm2 9.9 x 6
  • Controlled Baseline — One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of Up to -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • 400-Mbps Signaling Rate(2) and 200-Mxfr/s Data Transfer Rate
  • Operates With a Single 3.3-V Supply
  • -4-V to 5-V Common-Mode Input Voltage Range
  • Differential Input Thresholds < ±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
  • Integrated 110- Line Termination Resistors On LVDT Products
  • Complies With TIA/EIA-644 (LVDS)
  • Active Failsafe Assures a High-Level Output With No Input
  • Bus-Pin ESD Protection Exceeds 15-kV HBM
  • Input Remains High-Impedance On Power Down
  • TTL Inputs Are 5-V Tolerant
  • Pin-Compatible With the AM26LS32, SN65LVDS32B, μA9637, SN65LVDS9637B

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
(2) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
  • Controlled Baseline — One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of Up to -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • 400-Mbps Signaling Rate(2) and 200-Mxfr/s Data Transfer Rate
  • Operates With a Single 3.3-V Supply
  • -4-V to 5-V Common-Mode Input Voltage Range
  • Differential Input Thresholds < ±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
  • Integrated 110- Line Termination Resistors On LVDT Products
  • Complies With TIA/EIA-644 (LVDS)
  • Active Failsafe Assures a High-Level Output With No Input
  • Bus-Pin ESD Protection Exceeds 15-kV HBM
  • Input Remains High-Impedance On Power Down
  • TTL Inputs Are 5-V Tolerant
  • Pin-Compatible With the AM26LS32, SN65LVDS32B, μA9637, SN65LVDS9637B

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
(2) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15-kV human-body model (HBM) and ±600-V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS33-EP is characterized for operation from -55°C to 125°C.

This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15-kV human-body model (HBM) and ±600-V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS33-EP is characterized for operation from -55°C to 125°C.
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頂層文檔 類型 標(biāo)題 格式選項(xiàng) 下載最新的英語版本 日期
* 數(shù)據(jù)表 SN65LVDS33-EP High-Speed Differential Receivers 數(shù)據(jù)表 (Rev. B) 2007年 4月 19日
* VID SN65LVDS33-EP VID V6205614 2016年 6月 21日
* 輻射與可靠性報(bào)告 SN65LVDS33MDREP Reliability Report 2013年 9月 6日
應(yīng)用簡報(bào) LVDS to Improve EMC in Motor Drives 2018年 9月 27日
應(yīng)用簡報(bào) How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
應(yīng)用簡報(bào) How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日

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評估板

SN65LVDS31-33EVM — 用于 SN65LVDS31 和 SN65LVDS33 的評估模塊

TI offers a series of low-voltage differential signaling (LVDS) evaluation modules (EVMs) designed for analysis of the electrical characteristics of LVDS drivers and receivers. Four unique EVMs are available to evaluate the different classes of LVDS devices offered by TI.

As seen in the Combination (...)

用戶指南: PDF
TI.com 上無現(xiàn)貨
仿真模型

SN65LVDS33 IBIS Model (Rev. A)

SLLC069A.ZIP (6 KB) - IBIS Model
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TINA-TI — 基于 SPICE 的模擬仿真程序

TINA-TI 提供了 SPICE 所有的傳統(tǒng)直流、瞬態(tài)和頻域分析以及更多。TINA 具有廣泛的后處理功能，允許您按照希望的方式設(shè)置結(jié)果的格式。虛擬儀器允許您選擇輸入波形、探針電路節(jié)點(diǎn)電壓和波形。TINA 的原理圖捕獲非常直觀 - 真正的“快速入門”。

TINA-TI 安裝需要大約 500MB。直接安裝，如果想卸載也很容易。我們相信您肯定會愛不釋手。

TINA 是德州儀器 (TI) 專有的 DesignSoft 產(chǎn)品。該免費(fèi)版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需獲取可用 TINA-TI 模型的完整列表，請參閱：SpiceRack - 完整列表 

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用戶指南: PDF
英語版 (Rev.A): PDF
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包含信息：
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  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
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