SN55LVDS33-SP

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高速差動接收器

產品詳情

Function Receiver Protocols CML, LVDS, LVPECL, PECL Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL Output signal LVTTL Rating Space Operating temperature range (°C) -55 to 125
Function Receiver Protocols CML, LVDS, LVPECL, PECL Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL Output signal LVTTL Rating Space Operating temperature range (°C) -55 to 125
CFP (W) 16 69.319 mm2 10.3 x 6.73
  • 400-Mbps Signaling Rate and 200-Mxfr/s Data Transfer Rate The signaling rate
    of a line is the number of voltage transitions that are made per second expressed
    in the units bps (bits per second).
  • Operates With a Single 3.3-V Supply
  • –4 V to 5 V Common-Mode Input Voltage Range
  • Differential Input Thresholds < ±50 mV With 50 mV of Hysteresis Over Entire
    Common-Mode Input Voltage Range
  • Complies With TIA/EIA-644 (LVDS)
  • Active Failsafe Assures a High-Level Output With No Input
  • Bus-Pin ESD Protection Exceeds 15-kV HBM
  • Input Remains High-Impedance On Power Down
  • TTL Inputs Are 5-V Tolerant
  • QML-V Qualified, SMD 5962-07248
  • Military Temperature Range (–55°C to 125°C)

  • 400-Mbps Signaling Rate and 200-Mxfr/s Data Transfer Rate The signaling rate
    of a line is the number of voltage transitions that are made per second expressed
    in the units bps (bits per second).
  • Operates With a Single 3.3-V Supply
  • –4 V to 5 V Common-Mode Input Voltage Range
  • Differential Input Thresholds < ±50 mV With 50 mV of Hysteresis Over Entire
    Common-Mode Input Voltage Range
  • Complies With TIA/EIA-644 (LVDS)
  • Active Failsafe Assures a High-Level Output With No Input
  • Bus-Pin ESD Protection Exceeds 15-kV HBM
  • Input Remains High-Impedance On Power Down
  • TTL Inputs Are 5-V Tolerant
  • QML-V Qualified, SMD 5962-07248
  • Military Temperature Range (–55°C to 125°C)

These LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mV over the full input common-mode voltage range.

The receivers can withstand ±15-kV Human-Body Model (HBM) and ±600-V Machine Model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN55LVDS33 is characterized for operation from –55°C to 125°C.

These LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mV over the full input common-mode voltage range.

The receivers can withstand ±15-kV Human-Body Model (HBM) and ±600-V Machine Model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN55LVDS33 is characterized for operation from –55°C to 125°C.

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類型 標題 下載最新的英語版本 日期
* 數據表 High-Speed Differential Receiver 數據表 (Rev. C) 2012年 3月 1日
* SMD SN55LVDS33-SP SMD 5962-07248 2016年 7月 8日
* 輻射與可靠性報告 SN55LVDS33-SP 50-krad and 100-krad TID Report 2015年 3月 31日
* 輻射與可靠性報告 SN55LVDS33-SP SEE Report 2015年 3月 31日
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應用手冊 單粒子效應置信區間計算 (Rev. A) PDF | HTML 英語版 (Rev.A) PDF | HTML 2022年 12月 2日
電子書 電子產品輻射手冊 (Rev. B) 2022年 5月 7日
應用簡報 航天級 100krad 隔離式串行外設接口 (SPI) LVDS 電路 英語版 PDF | HTML 2021年 9月 7日
電子書 電子產品輻射手冊 (Rev. A) 2019年 5月 21日

設計和開發

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仿真模型

SN55LVDS33-SP IBIS MODEL

SLYM089.ZIP (6 KB) - IBIS Model
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用戶指南: PDF
英語版 (Rev.A): PDF
封裝 引腳 CAD 符號、封裝和 3D 模型
CFP (W) 16 Ultra Librarian

訂購和質量

包含信息:
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息:
  • 制造廠地點
  • 封裝廠地點

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