LP2997

正在供貨

DDR-II 終止穩壓器

產品詳情

Product type DDR Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.822 Vout (max) (V) 0.887 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 DDR memory type DDR2
Product type DDR Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.822 Vout (max) (V) 0.887 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 DDR memory type DDR2
HSOIC (DDA) 8 29.4 mm2 4.9 x 6 SOIC (D) 8 29.4 mm2 4.9 x 6
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • Available in SOIC-8, SO PowerPAD-8 Packages

All trademarks are the property of their respective owners.

  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • Available in SOIC-8, SO PowerPAD-8 Packages

All trademarks are the property of their respective owners.

The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
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LP2996-N 正在供貨 具有 DDR2 關斷引腳的 1.5A DDR 終端穩壓器 DDR-I And DDR-II Linear Termination Regulator

技術文檔

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類型 標題 下載最新的英語版本 日期
* 數據表 LP2997 DDR-II Termination Regulator 數據表 (Rev. F) 2013年 4月 4日
應用手冊 Limiting DDR Termination Regulators’ Inrush Current 2016年 8月 23日
應用手冊 AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) 2013年 5月 6日

設計和開發

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仿真模型

LP2997 PSpice Transient Model

SNVMAH7.ZIP (70 KB) - PSpice Model
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仿真模型

LP2997 Unencrypted PSpice Transient Model

SNVMAH8.ZIP (4 KB) - PSpice Model
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參考設計

TIDA-010011 — 適用于保護繼電器處理器模塊的高效電源架構參考設計

該參考設計展示了各種電源架構，這些架構可為需要 >1A 負載電流和高效率的應用處理器模塊生成多個電壓軌。所需的電源通過來自背板的 5V、12V 或 24V 直流輸入生成。電源通過帶集成 FET 的直流/直流轉換器生成并且使用帶集成電感器的電源模塊以減小尺寸。此設計采用 HotRod? 封裝類型，適用于需要低 EMI 的應用，也非常適合設計時間受限的應用。其他功能包括 DDR 端接穩壓器、輸入電源 OR-ing、電壓時序控制、過載保護電子保險絲以及電壓和負載電流監控。該設計可以用于處理器、數字信號處理器和現場可編程門陣列。該設計已依照 CISPR22 標準針對輻射發射進行了測試，符合 A (...)
原理圖: PDF
封裝 引腳 CAD 符號、封裝和 3D 模型
HSOIC (DDA) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian

訂購和質量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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