CDCM7005-SP

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耐輻射加固保障 (RHA) 3.3V 高性能時(shí)鐘抖動(dòng)清除器和同步器

產(chǎn)品詳情

Function Single-loop PLL Number of outputs 5 Output frequency (min) (MHz) 0 Output frequency (max) (MHz) 1500 Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Output type LVCMOS, LVPECL Supply voltage (min) (V) 3 Supply voltage (max) (V) 3.6 Features Programmable Delay Rating Space Operating temperature range (°C) -55 to 125 Number of input channels 2
Function Single-loop PLL Number of outputs 5 Output frequency (min) (MHz) 0 Output frequency (max) (MHz) 1500 Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Output type LVCMOS, LVPECL Supply voltage (min) (V) 3 Supply voltage (max) (V) 3.6 Features Programmable Delay Rating Space Operating temperature range (°C) -55 to 125 Number of input channels 2
CFP (HFG) 52 363.474225 mm2 19.065 x 19.065
  • High Performance LVPECL and LVCMOS PLL
    Clock Synchronizer
  • Two Reference Clock Inputs (Primary and
    Secondary Clock) for Redundancy Support
    With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies Up to
    200 MHz
  • VCXO_IN Clock is Synchronized to One of the
    Two Reference Clocks
  • VCXO_IN Frequencies Up to 2 GHz (LVPECL)
  • Outputs can be a Combination of LVPECL and
    LVCMOS (Up to Five Differential LVPECL
    Outputs or Up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by x1, /2, /3, /4,
    /6, /8, /16 on Each Output
    Individually
  • Efficient Jitter Cleaning from Low PLL Loop
    Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and
    SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 μA to 3 mA
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-
    Ended Input Signals (VCXO_IN)
  • Frequency Hold Over Mode Improves Fail-Safe
    Operation
  • Power-Up Control Forces LVPECL Outputs to Tri-
    State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • High-Performance 52 Pin Ceramic Quad Flat
    Pack (HFG)
  • Rad-Tolerant : 50 kRad (Si) TID
  • QML-V Qualified, SMD 5962-07230
  • Military Temperature Range: –55°C to 125°C Tcase
  • Engineering Evaluation (/EM) Samples are
    Available(1)
  • High Performance LVPECL and LVCMOS PLL
    Clock Synchronizer
  • Two Reference Clock Inputs (Primary and
    Secondary Clock) for Redundancy Support
    With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies Up to
    200 MHz
  • VCXO_IN Clock is Synchronized to One of the
    Two Reference Clocks
  • VCXO_IN Frequencies Up to 2 GHz (LVPECL)
  • Outputs can be a Combination of LVPECL and
    LVCMOS (Up to Five Differential LVPECL
    Outputs or Up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by x1, /2, /3, /4,
    /6, /8, /16 on Each Output
    Individually
  • Efficient Jitter Cleaning from Low PLL Loop
    Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and
    SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 μA to 3 mA
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-
    Ended Input Signals (VCXO_IN)
  • Frequency Hold Over Mode Improves Fail-Safe
    Operation
  • Power-Up Control Forces LVPECL Outputs to Tri-
    State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • High-Performance 52 Pin Ceramic Quad Flat
    Pack (HFG)
  • Rad-Tolerant : 50 kRad (Si) TID
  • QML-V Qualified, SMD 5962-07230
  • Military Temperature Range: –55°C to 125°C Tcase
  • Engineering Evaluation (/EM) Samples are
    Available(1)

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).
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類(lèi)型 標(biāo)題 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner 數(shù)據(jù)表 (Rev. G) PDF | HTML 2015年 12月 3日
* 輻射與可靠性報(bào)告 CDCM7005-SP Single-Event Effects Report 2025年 6月 4日
* SMD CDCM7005-SP SMD 5962-07230 2016年 7月 8日
* 輻射與可靠性報(bào)告 CDCM7005MHFG-V Radiation Test Report 2014年 11月 12日
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選擇指南 TI Space Products (Rev. K) 2025年 4月 4日
更多文獻(xiàn)資料 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025年 2月 20日
應(yīng)用手冊(cè) 單粒子效應(yīng)置信區(qū)間計(jì)算 (Rev. A) PDF | HTML 英語(yǔ)版 (Rev.A) PDF | HTML 2022年 12月 2日
電子書(shū) 電子產(chǎn)品輻射手冊(cè) (Rev. B) 2022年 5月 7日
電子書(shū) 電子產(chǎn)品輻射手冊(cè) (Rev. A) 2019年 5月 21日
EVM 用戶(hù)指南 CDCM7005EVM-CVAL Evaluation Module (EVM) User's Guide 2018年 9月 11日
應(yīng)用手冊(cè) Phase Noise/Phase Jitter Performance of CDCM7005 2005年 7月 26日

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CDCM7005EVM-CVAL — CDCM7005-SP 評(píng)估模塊

CDCM7005 是一款高性能、低相位噪聲、低偏差的時(shí)鐘同步器，可將板載電壓控制晶體振蕩器 (VC(X)O) 頻率與外部參考時(shí)鐘保持同步。該器件的運(yùn)行頻率高達(dá) 2 GHz。PLL 環(huán)路帶寬和阻尼因數(shù)可進(jìn)行調(diào)節(jié)以滿足不同的系統(tǒng)需求，方法是選擇外部 VC(X)O、環(huán)路濾波器組件、PFD 的頻率以及電荷泵電流。五個(gè)差動(dòng) LVPECL 和五個(gè) LVCMOS 對(duì)輸出中的每一個(gè)均可通過(guò)串行外設(shè)接口 (SPI) 進(jìn)行編程。該 SPI 可以單獨(dú)控制頻率和啟用/禁用每個(gè)輸出的狀態(tài)。由于系統(tǒng)需要使用外部組件（例如，環(huán)路濾波器和 VC(X)O），因此該 EVM (...)
用戶(hù)指南: PDF
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評(píng)估模塊 (EVM) 用 GUI

SGLC002 — CDCM7005-SP EVM GUI

支持的產(chǎn)品和硬件

支持的產(chǎn)品和硬件

產(chǎn)品
時(shí)鐘抖動(dòng)清除器
CDCM7005-SP — 耐輻射加固保障 (RHA) 3.3V 高性能時(shí)鐘抖動(dòng)清除器和同步器
硬件開(kāi)發(fā)
評(píng)估板
CDCM7005EVM-CVAL — CDCM7005-SP 評(píng)估模塊
仿真模型

CDCM7005-SP IBIS MODEL A

SLLM295.ZIP (36 KB) - IBIS Model
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仿真模型

CDCM7005-SP IBIS MODEL B

SLLM296.ZIP (36 KB) - IBIS Model
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仿真模型

CDCM7005-SP IBIS MODEL C

SLLM297.ZIP (36 KB) - IBIS Model
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