產品詳情

Function Clock divider, Clock multiplier, Clock synthesizer Number of outputs 6 Output frequency (max) (MHz) 167 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type Differential, LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) 0 to 70 Features I2C, Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Function Clock divider, Clock multiplier, Clock synthesizer Number of outputs 6 Output frequency (max) (MHz) 167 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type Differential, LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) 0 to 70 Features I2C, Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 20 41.6 mm2 6.5 x 6.4
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • EEPROM Programming Without the Need to Apply High Programming Voltage
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typ 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock?)
  • Packaged in 20-Pin TSSOP

Pro-Clock is a trademark of Texas Instruments.

  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • EEPROM Programming Without the Need to Apply High Programming Voltage
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typ 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock?)
  • Packaged in 20-Pin TSSOP

Pro-Clock is a trademark of Texas Instruments.

The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE906 is characterized for operation from 0°C to 70°C.

The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE906 is characterized for operation from 0°C to 70°C.

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技術文檔

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類型 標題 下載最新的英語版本 日期
* 數據表 Programmable 3-PLL Clock Synthesizer / Multiplier/Divider 數據表 (Rev. H) 2007年 12月 11日
應用手冊 High Speed Layout Guidelines (Rev. A) 2017年 8月 8日
用戶指南 CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 2010年 11月 22日
應用手冊 Troubleshooting I2C Bus Protocol 2009年 10月 19日
用戶指南 CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual 2008年 12月 9日
應用手冊 CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A) 2007年 11月 28日
EVM 用戶指南 CDCE906/CDCE706 Programming EVM (Rev. B) 2007年 8月 14日
用戶指南 CDCE906/CDCE706 Performance EVM (Rev. B) 2007年 4月 17日
應用手冊 Clock Recommendations for the DM643x EVM 2006年 11月 29日
應用手冊 Recommended Terminations for the Differential Inputs of CDCE906/CDCE706 2006年 8月 10日

設計和開發

如需其他信息或資源,請點擊以下任一標題進入詳情頁面查看(如有)。

評估板

CDCE906-706PERFEVM — CDCE906 和 CDCE706 評估模塊

CDCE906-706PERF 評估模塊可驗證具有晶振差分輸入和 LVCMOS 輸入選項的 CDCE906 和 CDCE706 的功能和性能。可以通過 SMA 電纜將六個輸出直接連接到示波器。
用戶指南: PDF
TI.com 上無現貨
評估板

CDCE906-706PROGEVM — CDCE906 和 CDCE706 可編程 EVM

用戶指南: PDF
TI.com 上無現貨
應用軟件和框架

SCAC097 Executable File Without LabVIEW 8.2 Run Time Engine

支持的產品和硬件

支持的產品和硬件

產品
時鐘發生器
CDCE706 300MHz、LVCMOS、可編程 3-PLL 時鐘合成器/倍頻器/分頻器 CDCE906 167MHz、LVCMOS、可編程 3-PLL 時鐘合成器/倍頻器/分頻器 CDCE913 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 1-PLL VCXO 時鐘合成器 CDCE925 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 2-PLL VCXO 時鐘合成器 CDCE937 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 3-PLL VCXO 時鐘合成器 CDCE949 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 4-PLL VCXO 時鐘合成器
支持軟件

CLOCKPRO ClockPro Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:

  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

支持的產品和硬件

支持的產品和硬件

產品
時鐘發生器
CDCE706 300MHz、LVCMOS、可編程 3-PLL 時鐘合成器/倍頻器/分頻器 CDCE906 167MHz、LVCMOS、可編程 3-PLL 時鐘合成器/倍頻器/分頻器 CDCE913 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 1-PLL VCXO 時鐘合成器 CDCE925 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 2-PLL VCXO 時鐘合成器 CDCE937 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 3-PLL VCXO 時鐘合成器 CDCE949 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 4-PLL VCXO 時鐘合成器 CDCEL913 具有 1.8V LVCMOS 輸出的可編程 1-PLL VCXO 時鐘合成器 CDCEL925 具有 1.8V LVCMOS 輸出的可編程 2-PLL VCXO 時鐘合成器 CDCEL937 具有 1.8V LVCMOS 輸出的可編程 3-PLL VCXO 時鐘合成器 CDCEL949 具有 1.8V LVCMOS 輸出的可編程 4-PLL VCXO 時鐘合成器
硬件開發
評估板
CDCE906-706PROGEVM CDCE906 和 CDCE706 可編程 EVM CDCE913PERF-EVM CDCE913 性能評估模塊 CDCE925PERF-EVM CDCE925 性能評估模塊 CDCE949PERF-EVM CDCE949 性能評估模塊 CDCEL913PERF-EVM CDCEL913 性能評估模塊 CDCEL925PERF-EVM CDCEL925 性能評估模塊 CDCEL949PERF-EVM CDCEL949 性能評估模塊 CDCEL9XXPROGEVM CDCE(L)949 系列 EEPROM 編程板
軟件
軟件編程工具
CLOCKPRO ClockPro™ 程序設計軟件
支持軟件

SCAC073 TI-Pro-Clock Programming Software

支持的產品和硬件

支持的產品和硬件

產品
時鐘發生器
CDC706 200MHz、LVCMOS、定制編程的 3-PLL 時鐘合成器、倍頻器和分頻器 CDC906 167MHz、LVCMOS、定制編程的 3-PLL 時鐘合成器、倍頻器和分頻器 CDCE706 300MHz、LVCMOS、可編程 3-PLL 時鐘合成器/倍頻器/分頻器 CDCE906 167MHz、LVCMOS、可編程 3-PLL 時鐘合成器/倍頻器/分頻器 CDCE913 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 1-PLL VCXO 時鐘合成器 CDCE925 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 2-PLL VCXO 時鐘合成器 CDCE937 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 3-PLL VCXO 時鐘合成器 CDCE949 具有 2.5V 或 3.3V LVCMOS 輸出的可編程 4-PLL VCXO 時鐘合成器 CDCEL913 具有 1.8V LVCMOS 輸出的可編程 1-PLL VCXO 時鐘合成器 CDCEL925 具有 1.8V LVCMOS 輸出的可編程 2-PLL VCXO 時鐘合成器 CDCEL937 具有 1.8V LVCMOS 輸出的可編程 3-PLL VCXO 時鐘合成器 CDCEL949 具有 1.8V LVCMOS 輸出的可編程 4-PLL VCXO 時鐘合成器
仿真模型

CDCE906 IBIS Model (Rev. A)

SCAC071A.ZIP (119 KB) - IBIS Model
光繪文件

CDCE906/CDCE706 PERF EVM Gerber Files

SCAC074.ZIP (963 KB)
光繪文件

CDCE906/CDCE706 PROG EVM Gerber files

SCAC075.ZIP (847 KB)
模擬工具

PSPICE-FOR-TI — PSpice? for TI 設計和仿真工具

PSpice? for TI 可提供幫助評估模擬電路功能的設計和仿真環境。此功能齊全的設計和仿真套件使用 Cadence? 的模擬分析引擎。PSpice for TI 可免費使用,包括業內超大的模型庫之一,涵蓋我們的模擬和電源產品系列以及精選的模擬行為模型。

借助?PSpice for TI 的設計和仿真環境及其內置的模型庫,您可對復雜的混合信號設計進行仿真。創建完整的終端設備設計和原型解決方案,然后再進行布局和制造,可縮短產品上市時間并降低開發成本。?

在?PSpice for TI 設計和仿真工具中,您可以搜索 TI (...)
參考設計

TIDA-00080 — 具有 Δ-Σ 調制器的基于分流器的隔離型電流感應模塊參考設計

這種基于分流器的隔離式電流測量單元無需使用電流互感器 (CT) 即可實現高精度電流測量。通過整合了高壓隔離功能和 Delta-Sigma 調制器的 AMC1304 來實現隔離。此解決方案避免了使用 CT 的必要,這是客戶十分重視的一點,因為這可以減小電路板尺寸、降低產品重量、減輕系統中的串擾和 EMI,此外通過將 CT 替換為分流器可減少機械問題,從而潛在延長產品使用壽命。
設計指南: PDF
原理圖: PDF
參考設計

TIDA-00171 — 隔離式電流分流和電壓測量參考設計

此評估套件和參考設計在 C2000? TMS320F28377D Delfino? 微控制器中實現了 AMC130x 加強版隔離式 Delta-Sigma 調制器以及集成式正弦濾波器。此設計讓您能夠評估這些測量值的性能:三個電機電流、三個逆變器電壓以及直流鏈路電壓。套件中提供了固件來配置正弦濾波器、設置 PLL 頻率以及接收來自正弦濾波器的數據。此外,還提供一個多功能運行時 GUI 來幫助用戶驗證 AMC130x 性能,并支持 Delfino 控制器中的正弦濾波器參數的配置更改。
用戶指南: PDF
原理圖: PDF
英語版 (Rev.A): PDF
封裝 引腳 CAD 符號、封裝和 3D 模型
TSSOP (PW) 20 Ultra Librarian

訂購和質量

包含信息:
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續可靠性監測
包含信息:
  • 制造廠地點
  • 封裝廠地點

推薦產品可能包含與 TI 此產品相關的參數、評估模塊或參考設計。

支持和培訓

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