產(chǎn)品詳情

Function Single-ended Output frequency (max) (MHz) 100 Number of outputs 10 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 2500 Features 1:10 fanout Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Output type LVTTL Input type LVTTL
Function Single-ended Output frequency (max) (MHz) 100 Number of outputs 10 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 2500 Features 1:10 fanout Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Output type LVTTL Input type LVTTL
SSOP (DB) 24 63.96 mm2 8.2 x 7.8
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • LVTTL-Compatible Inputs and Outputs
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Distributes One Clock Input to 10 Outputs
  • Outputs Have Internal Series Damping Resistor to Reduce Transmission Line Effects
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • State-of-the-Art EPIC-IIB? BiCMOS Design Significantly Reduces Power Dissipation
  • Shrink Small-Outline (DB) Package

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
EPIC-IIB is a trademark of Texas Instruments.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • LVTTL-Compatible Inputs and Outputs
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Distributes One Clock Input to 10 Outputs
  • Outputs Have Internal Series Damping Resistor to Reduce Transmission Line Effects
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • State-of-the-Art EPIC-IIB? BiCMOS Design Significantly Reduces Power Dissipation
  • Shrink Small-Outline (DB) Package

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
EPIC-IIB is a trademark of Texas Instruments.

The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to 10 outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351 operates at nominal 3.3-V VCC.

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.

The CDC2351M is characterized for operation over the full military temperature range of –55°C to 125°C.

The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to 10 outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351 operates at nominal 3.3-V VCC.

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.

The CDC2351M is characterized for operation over the full military temperature range of –55°C to 125°C.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 CDC2351-EP: 1-Line to 10-Line Clock Driver w/3-State Outputs 數(shù)據(jù)表 (Rev. A) 2004年 8月 24日
* VID CDC2351-EP VID V6204757 2016年 6月 21日
* 輻射與可靠性報告 CDC2351MDBREP Reliability Report 2011年 8月 25日

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SSOP (DB) 24 Ultra Librarian

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