ZHCSF24 May 2016 TDC7201
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Register Initialization
- 7.6.2 TDCx_CONFIG1: TDCx Configuration Register 1 R/W (address = 00h, CSBx asserted) [reset = 0h]
- 7.6.3 TDCx_CONFIG2: TDCx Configuration Register 2 R/W (address = 01h, CSBx asserted) [reset = 40h]
- 7.6.4 TDCx_INT_STATUS: Interrupt Status Register (address = 02h, CSBx asserted) [reset = 00h]
- 7.6.5 TDCx_INT_MASK: TDCx Interrupt Mask Register R/W (address = 03h, CSBx asserted) [reset = 07h]
- 7.6.6 TDCx_COARSE_CNTR_OVF_H: Coarse Counter Overflow High Value Register (address = 04h, CSBx asserted) [reset = FFh]
- 7.6.7 TDCx_COARSE_CNTR_OVF_L: TDCx Coarse Counter Overflow Low Value Register (address = 05h, CSBx asserted) [reset = FFh ]
- 7.6.8 TDCx_CLOCK_CNTR_OVF_H: Clock Counter Overflow High Register (address = 06h, CSBx asserted) [reset = FFh]
- 7.6.9 TDCx_CLOCK_CNTR_OVF_L: Clock Counter Overflow Low Register (address = 07h, CSBx asserted) [reset = FFh]
- 7.6.10 TDCx_CLOCK_CNTR_STOP_MASK_H: CLOCK Counter STOP Mask High Value Register (address = 08h, CSBx asserted) [reset = 00h]
- 7.6.11 TDCx_CLOCK_CNTR_STOP_MASK_L: CLOCK Counter STOP Mask Low Value Register (address = 09h, CSBx asserted) [reset = 00h]
- 7.6.12 TDCx_TIME1: Time 1 Register (address: 10h, CSBx asserted) [reset = 00_0000h]
- 7.6.13 TDCx_CLOCK_COUNT1: Clock Count Register (address: 11h, CSBx asserted) [reset = 00_0000h]
- 7.6.14 TDCx_TIME2: Time 2 Register (address: 12h, CSBx asserted) [reset = 00_0000h]
- 7.6.15 TDCx_CLOCK_COUNT2: Clock Count Register (address: 13h, CSBx asserted) [reset = 00_0000h]
- 7.6.16 TDCx_TIME3: Time 3 Register (address: 14h, CSBx asserted) [reset = 00_0000h]
- 7.6.17 TDCx_CLOCK_COUNT3: Clock Count Registers (address: 15h, CSBx asserted) [reset = 00_0000h]
- 7.6.18 TDCx_TIME4: Time 4 Register (address: 16h, CSBx asserted) [reset = 00_0000h]
- 7.6.19 TDCx_CLOCK_COUNT4: Clock Count Register (address: 17h, CSBx asserted) [reset = 00_0000h]
- 7.6.20 TDCx_TIME5: Time 5 Register (address: 18h, CSBx asserted) [reset = 00_0000h]
- 7.6.21 TDCx_CLOCK_COUNT5: Clock Count Register (address: 19h, CSBx asserted) [reset = 00_0000h]
- 7.6.22 TDCx_TIME6: Time 6 Register (address: 1Ah, CSBx asserted) [reset = 00_0000h]
- 7.6.23 TDCx_CALIBRATION1: Calibration 1 Register (address: 1Bh, CSBx asserted) [reset = 00_0000h]
- 7.6.24 TDCx_CALIBRATION2: Calibration 2 Register (address: 1Ch, CSBx asserted) [reset = 00_0000h]
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
1 特性
- 分辨率：55ps
- 標準偏差：35ps
- 測量范圍:
- 獨立模式 1：12ns 至 2000ns
- 獨立模式 2：250ns 至 8ms
- 組合模式：0.25ns 至 8ms
- 低運行功耗：2.7mA
- 最多支持 10 個 STOP 信號
- 自主多周期平均模式，可實現低功耗
- 電源電壓：2V 至 3.6V
- 工作溫度范圍：-40°C 至 +85°C
- 用于寄存器訪問的串行外設接口 (SPI) 接口
2 應用
- 測距儀
- 激光雷達
- 無人機和機器人
- 高級駕駛員輔助系統 (ADAS)
- 沖突檢測系統
- 流量計
3 說明
TDC7201 設計為與采用飛行時間技術的超聲波、激光和雷達測距設備搭配使用。TDC7201 內置有兩個時間數字轉換器 (TDC)，可用于測量 4 厘米到數千米范圍內的距離，而且架構非常簡單，無需使用昂貴的現場可編程門陣列 (FPGA) 或處理器。
每個 TDC 均可執行秒表功能，測量 START 脈沖與多達 5 個 STOP 脈沖之間的時間間隔（飛行時間，即 TOF）。利用這兩個 TDC，可以同時且單獨測量兩對 START 和 STOP 引腳，從而提高時間測量設計的靈活性。
該器件內置自校準時基，可對時間和溫度偏差進行補償。這一自校準功能使得時間數字轉換器能夠獲得皮秒級精度。這一精度使得 TDC7201 非常適合測距 應用。
當 TDC7201 器件置于自主多周期平均模式下時，可降低系統功耗，非常適合電池供電式流量計。在該模式下，主器件會進入休眠模式以實現節能并在測量序列完成后由 TDC 中斷喚醒。
器件信息(1)
| 器件型號 | 封裝 | 封裝尺寸（標稱值） |
|---|---|---|
| TDC7201 | nFBGA (25) | 4.00mm x 4.00mm |
- 要了解所有可用封裝，請見數據表末尾的可訂購產品附錄。
簡化的激光雷達應用框圖
