7.3.1 LDO

The LDO (low-dropout) is an internal supply voltage regulator for the TDC7201. Each of the two TDC cores of the TDC7201 has its own dedicated LDO. No external circuitry needs to be connected to the output of this regulator other than the mandatory external decoupling capacitor on VREG1 and VREG2.

Recommendations for the decoupling capacitor parameters:

• Type: ceramic
• Capacitance: 0.4 µF to 2.7 µF (1 µF typical). If using a capacitor value outside the recommended range, the part may malfunction and can be damaged.
• ESR: 100 mΩ (maximum)

7.3.2 CLOCK

The TDC7201 needs an external reference clock connected to the CLOCK pin. This external clock input serves as the reference clock for both TDCs of the TDC7201. The external CLOCK is used to calibrate the internal time base accurately and therefore, the measurement accuracy is heavily dependent on the external CLOCK accuracy. This reference clock is also used by all digital circuits inside the device; thus, CLOCK has to be available and stable at all times when the device is enabled (ENABLE = HIGH).

Figure 20 shows the typical effect of the external CLOCK frequency on the measurement uncertainty. With a reference clock of 1 MHz, the standard deviation of a set of measurement results is approximately 243 ps. As the reference clock frequency is increased, the standard deviation (or measurement uncertainty) reduces. Therefore, using a reference clock of 16 MHz is recommended for optimal performance.

Figure 20. Standard Deviation vs CLOCK

7.3.3 Counters

7.4.1 Calibration

The time measurements performed by each TDCx of the TDC7201 are based on an internal time base which is represented as the LSB value of the TDCx_TIME1 to TDCx_TIME6 results registers. The typical LSB value can be seen in Electrical Characteristics. However, the actual value of the LSB can vary depending on environmental variables (temperature, systematic noise, and so forth). This variation can introduce significant error into the measurement result. There is also an offset error in the measurement due to certain internal delays in the device.

In order to compensate for these errors and to calculate the actual LSB value, calibration needs to be performed. The TDCx calibration consists of two measurement cycles of the external CLOCK. The first is a measurement of a single clock cycle period of the external clock; the second measurement is for the number of external CLOCK periods set by the CALIBRATION2_PERIODS in the TDCx_CONFIG2 register. The results from the calibration measurements are stored in the TDCx_CALIBRATION1 and TDCx_CALIBRATION2 registers.

The two-point calibration is used to determine the actual LSB in real time in order to convert the TDCx_TIME1 to TDCx_TIME6 results from number of delays to a real TOF number. Calibration is automatic and performed every time after a measurement and before measurement completion interrupt is sent to the MCU through INTBx pin. Only if a measurement is interrupted (for example, due to counter overflow or missing STOP signal), calibration is not performed. As discussed in the next sections, the calibrations will be used for calculating TOF in measurement modes 1 and 2.

7.4.2 Measurement Modes

7.4.2.1 Measurement Mode 1

In measurement mode 1, as shown in Figure 21, each TDCx of the TDC7201 performs the entire counting from START to the last STOP using its internal ring oscillator plus coarse counter. This method is recommended for measuring shorter time durations of < 2000 ns. TI does not recommend using measurement mode 1 for measuring time > 2000 ns because this decreases accuracy of the measurement (as shown in Figure 22).

Figure 21. Measurement Mode 1

Figure 22. Measurement Mode 1 Standard Deviation vs Measured Time-of-Flight

7.4.2.1.1 Calculating Time-of-Flight (Measurement Mode 1)

For measurement mode 1, the TOF between the START to the n^th STOP can be calculated using Equation 1:

Equation 1.

where

• TOF_n [sec] = time-of-flight measurement from the START to the n^th STOP
• TIME_n = n^th TIME measurement given by the TIME1 to TIME6 registers
• normLSB [sec] = normalized LSB value from calibration
• CLOCKperiod [sec] = external CLOCK period
• CALIBRATION1 = TDCx_CALIBRATION1 register value = TDC count for first calibration cycle
• CALIBRATION2 = TDCx_CALIBRATION2 register value = TDC count for second calibration cycle
• CALIBRATION2_PERIODS = setting for the second calibration cycle; located in register TDCx_CONFIG2

For example, assume the time-of-flight between the START to the 1^st STOP is desired, and the following readouts were obtained:

• TDCx_CALIBRATION2 = 21121 (decimal)
• TDCx_CALIBRATION1 = 2110 (decimal)
• CALIBRATION2_PERIODS = 10
• CLOCK = 8 MHz
• TDCx_TIME1 = 4175 (decimal)

Therefore, the calculation for time-of-flight is:

• calCount = (21121 – 2110) / (10 – 1) = 2112.33
• normLSB = (1/8MHz) / (2112.33) = 59.17 ps
• TOF1 = (4175)(5.917 x 10^-11) = 247.061 ns

7.4.2.2 Measurement Mode 2

In measurement mode 2, the internal ring oscillator of each TDCx of the TDC7201 is used only to count fractional parts of the total measured time. As shown in Figure 23, the internal ring oscillator starts counting from when it receives the START signal until the first rising edge of the CLOCK. Then, the internal ring oscillator switches off, and the Clock counter starts counting the clock cycles of the external CLOCK input until a STOP pulse is received. The internal ring oscillator again starts counting from the STOP signal until the next rising edge of the CLOCK.

Figure 23. Measurement Mode 2

7.4.2.2.1 Calculating Time-of-Flight (TOF) (Measurement Mode 2)

The TOF between the START to the n^th STOP can be calculated using Equation 2:

Equation 2.

where

• TOF_n [sec] = time-of-flight measurement from the START to the n^th STOP
• TIME1 = TDCx_TIME1 register value = time 1 measurement given by the TDC7201 register address 0x10
• TIME_(n+1) = TDCx_TIME_(n+1) register value = (n+1) time measurement, where n = 1 to 5 (TDCx_TIME2 to TDCx_TIME6 registers)
• normLSB [sec] = normalized LSB value from calibration
• CLOCK_COUNT_n = nth clock count, where n = 1 to 5 (TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5)
• CLOCKperiod [sec] = external CLOCK period
• CALIBRATION1 = TDCx_CALIBRATION1 register value = TDC count for first calibration cycle
• CALIBRATION2 = TDCx_CALIBRATION2 register value = TDC count for second calibration cycle
• CALIBRATION2_PERIODS = setting for the second calibration; located in register TDCx_CONFIG2

For example, assume the time-of-flight between the START to the 1^st STOP is desired, and the following readouts were obtained:

• CALIBRATION2 = 23133 (decimal)
• CALIBRATION1 = 2315 (decimal)
• CALIBRATION2_PERIODS = 10
• CLOCK = 8 MHz
• TIME1 = 2147 (decimal)
• TIME2 = 201 (decimal)
• CLOCK_COUNT1 = 318 (decimal)

Therefore, the calculation for time-of-flight is:

Equation 3.

7.4.3 Timeout

For one STOP, each TDCx of the TDC7201 performs the measurement by counting from the START signal to the STOP signal. If no STOP signal is received, either the Clock Counter or Coarse Counter will overflow and will generate an interrupt (see Coarse and Clock Counters Overflow). If no START signal is received, the timer waits indefinitely for a START signal to arrive.

For multiple STOPs, each TDCx performs the measurement by counting from the START signal to the last STOP signal. All earlier STOP signals are captured and stored into the corresponding Measurement Results registers (TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1, TDCx_CALIBRATION2). The minimum time required between two consecutive STOP signals is defined in the Recommended Operating Conditions table. The device can be programmed to measure up to 5 STOP signals by setting the NUM_STOP bits in the TDCx_CONFIG2 register.

7.4.4 Multi-Cycle Averaging

In the Multi-Cycle Averaging Mode, the TDC7201 will perform a series of measurements on its own and will only send an interrupt to the MCU (for example, MSP430, C2000, and so forth) for wake up after the series has been completed. While waiting, the MCU can remain in sleep mode during the whole cycle (as shown in Figure 24).

Multi-Cycle Averaging Mode Setup and Conditions:

• The number of averaging cycles should be selected (1 to 128). This is done by programming the AVG_CYCLES bit in the TDCx_CONFIG2 register.
• The results of all measurements are reported in the Measurement Results registers (TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1, TDCx_CALIBRATION2 registers). The CLOCK_COUNTn registers should be right shifted by the log2(AVG_CYCLES) before calculating the TOF. For example, if using the multi-cycle averaging mode, Equation 2 should be rewritten as: TOFn = normLSB [TDCx_TIME1 - TDCx_TIME(n+1)] + [TDCx_CLOCK_COUNTn >> log 2 (AVG_CYCLES)] x [CLOCKperiod]
• Following each average cycle, the TDCx generates either a trigger event on the TRIGGx pin after the calibration measurement to commence a new measurement or an interrupt on the INTBx pin, indicating that the averaging sequence has completed.

This mode allows multiple measurements without MCU interaction, thus optimizing power consumption for the overall system.

Figure 24. Multi-Cycle Averaging Mode Example with 2 Averaging Cycles and 5 STOP Signals

7.4.5 START and STOP Edge Polarity

In order to achieve the highest measurement accuracy, having the same edge polarity for the START and STOP input signals is highly recommended. Otherwise, slightly different propagation delays due to symmetry shift between the rising and falling edge configuration will impact the measurement accuracy.

For highest measurement accuracy in measurement mode 2, TI recommends to choose for the START and STOP signal the rising edge. This is done by setting the START_EDGE and STOP_EDGE bits in the TDCx_CONFIG1 register to 0.

7.4.6 Measurement Sequence

The TDC7201 has two built-in TDCs with the capability to simultaneously and individually measure time delay on two pairs of START and STOP pins. Each TDCx is a stopwatch that measures time between a single event (edge on STARTx pin) and multiple subsequent events (edge on STOPx pin). The measurement sequence for each TDCx is as follows:

1. After powering up the device, the ENABLE pin needs to be low. There is one low to high transition required while VDD is supplied for correct initialization of the device.

NOTE

Pins VDD1 and VDD2 must be tied together at the board level and supplied from the same source.

2. MCU software requests new TDCx measurements to be initiated through the SPI™ interface.
3. After the start new measurement bit START_MEAS has been set in the TDCx_CONFIG1 register, the TDCx generates a trigger signal on the TRIGGx pin, which is typically used by the corresponding ultrasonic analog-front-end (such as the TDC1000) as start trigger for a measurement (for example, transmit signal for the ultrasonic burst).
4. Immediately after sending the trigger, the TDCx enables the STARTx pin and waits to receive the START pulse edge.
5. After receiving a START, the TDCx resets the TRIGGx pin.
6. The Clock counter is started after the next rising edge of the external clock signal (Measurement Mode 2). The Clock Counter STOP Mask registers (TDCx_CLOCK_CNTR_STOP_MASK_H and TDCx_CLOCK_CNTR_STOP_MASK_L) determine the length of the STOP mask window.
7. After reaching the Clock Counter STOP Mask value, the STOPx pin waits to receive a single or multiple STOP trigger signal from the analog-front-end (for example, detected echo signal of the ultrasonic burst signal).
8. After the last STOP trigger has been received, the TDCx will signal to the MCU through interrupt (INTBx pin) that there are new measurement results waiting in the registers. STARTx, STOPx and TRIGGx pins are disabled (in Multi-Cycle Averaging Mode, the TDCx will start the next cycle automatically by generating a new TRIGG signal). INTBx goes back to high whenever a new measurement is initiated through SPI or when the TDCx_INT_STATUS register bit NEW_MEAS_INT is cleared by writing a 1 to it.

NOTE

INTBx must be utilized to determine TDCx measurement completion; polling the TDCx_INT_STATUS register to determine measurement completion is NOT recommended as it will interfere with the TDCx measurement.

9. After the results are retrieved, the MCU can then start a new measurement with the same register settings. This is done by just setting the START_MEAS bit through SPI. It is not required to drive the ENABLE pin low between measurements.
10. The ENABLE pin can be taken low, if the time duration between measurements is long, and it is desired to put the TDC7201 in its lowest power state. However, upon taking ENABLE high again, the device will come up with its default register settings and will need to be configured through SPI.

The two TDCs of TDC7201 can be used independently to measure TOF. When used independently, the TDCx operation is as explained in the measurement sequence steps above. In this case, each TDCx has dedicated START, STOP inputs and measures their STARTx to STOPx time individually when the START_MEAS bit in the TDCx_CONFIG1 register is set. The MCU has to set up, control, and read the results from the two TDCs individually through the master SPI interface. To set up the registers and read back measurement results of TDCx, MCU needs to perform SPI read and write transactions with corresponding CSBx asserted.

7.4.7 Wait Times for TDC7201 Startup

The required wait time following the rising edge of the ENABLE pin of the TDC7201 is defined by three key times, as shown in Figure 25. All three times relate to the startup of the TDCx’s internal dedicated LDO, which is power gated when the device is disabled for optimal power consumption. The first parameter, T1_{SPI_RDY}, is the time after which the SPI interface is accessible. The second (T2_{LDO_SET1}) parameter and third (T3_{LDO_SET2}) parameter are related to the performance of a measurement made while the internal LDO is settling. The LDO supplies the TDC7201’s time measurement device, and a change in voltage on its supply during a measurement translates directly to an inaccuracy. It is therefore recommended to wait until the LDO is settled before time measurement begins.

The first time period relating to the measurement accuracy is T2_{LDO_SET1}, the LDO settling time 1. This is the time after which the LDO has settled to within 0.3% of its final value. A 0.3% error translates to a worst case time error (due to the LDO settling) of 0.3% × t_CLOCK, which is 375 ps in the case of an 8-MHz reference clock, or 187.5 ps if a 16-MHz clock is used. Finally, the time T3_{LDO_SET2} is the time after which the LDO has settled to its final value. For best performance, TI recommends that a time measurement is not started before T3_{LDO_SET2} to allow the LDO to fully settle. Typical times for these parameters are: T1_{SPI_RDY} is 100 µs, for T2_{LDO_SET1} is 300 µs, and for T3_{LDO_SET2} is 1.5 ms.

Figure 25. VREGx Startup Time

7.5.1 Serial Peripheral Interface (SPI)

The serial interface consists of data input (DIN), data output (DOUTx), serial interface clock (SCLK), and chip select bar (CSBx). The serial interface is used to configure the TDC7201 parameters available in various configuration registers.

The two TDCs of TDC7201 share the serial interface DIN and SCLK pins but support dedicated CSB and DOUT pins. Registers of the TDCx are selected for read/write access when their corresponding dedicated CSBx pin is asserted. By connecting together DOUT1 and DOUT2, a single SPI master interface of the MCU can be used to access both the TDC register sets by asserting the corresponding CSBx. Alternatively, by keeping DOUT1 and DOUT2 separate, data can be read out of the TDCs in parallel using their dedicated DOUTx pins. This doubles the data readout throughput but requires a second dedicated SPI interface of the MCU.

The communication on the SPI bus supports write and read transactions. A write transaction consists of a single write command byte, followed by single data byte. A read transaction consists of a single read command byte followed by 8 or 24 SCLK cycles. The write and read command bytes consist of a 1-bit auto-increment bit, a 1-bit read or write instruction, and a 6-bit register address. Figure 26 shows the SPI protocol for a transaction involving one byte of data (read or write).

Figure 26. SPI Protocol

7.6.1 Register Initialization

After power up (VDD supplied, ENABLE Pin low to high transition) the internal registers are initialized with the default value. Disabling the part by pulling ENABLE pin to GND will set the device into total shutdown. As the internal LDO is turned off settings in the register will be lost. The device initializes the registers with default values with the next enable (ENABLE pin to VDD).

Table 2. TDCx_ Register Summary⁽¹⁾

7.6.2 TDCx_CONFIG1: TDCx Configuration Register 1 R/W (address = 00h, CSBx asserted) [reset = 0h]

7.6.3 TDCx_CONFIG2: TDCx Configuration Register 2 R/W (address = 01h, CSBx asserted) [reset = 40h]

7.6.4 TDCx_INT_STATUS: Interrupt Status Register (address = 02h, CSBx asserted) [reset = 00h]

7.6.5 TDCx_INT_MASK: TDCx Interrupt Mask Register R/W (address = 03h, CSBx asserted) [reset = 07h]

A disabled interrupt will no longer be visible on the device pin (INTB). The interrupt bit in the TDCx_INT_STATUS register will still be active.

7.6.6 TDCx_COARSE_CNTR_OVF_H: Coarse Counter Overflow High Value Register (address = 04h, CSBx asserted) [reset = FFh]

7.6.7 TDCx_COARSE_CNTR_OVF_L: TDCx Coarse Counter Overflow Low Value Register (address = 05h, CSBx asserted) [reset = FFh ]

7.6.8 TDCx_CLOCK_CNTR_OVF_H: Clock Counter Overflow High Register (address = 06h, CSBx asserted) [reset = FFh]

7.6.9 TDCx_CLOCK_CNTR_OVF_L: Clock Counter Overflow Low Register (address = 07h, CSBx asserted) [reset = FFh]

7.6.10 TDCx_CLOCK_CNTR_STOP_MASK_H: CLOCK Counter STOP Mask High Value Register (address = 08h, CSBx asserted) [reset = 00h]

7.6.11 TDCx_CLOCK_CNTR_STOP_MASK_L: CLOCK Counter STOP Mask Low Value Register (address = 09h, CSBx asserted) [reset = 00h]

7.6.12 TDCx_TIME1: Time 1 Register (address: 10h, CSBx asserted) [reset = 00_0000h]

7.6.13 TDCx_CLOCK_COUNT1: Clock Count Register (address: 11h, CSBx asserted) [reset = 00_0000h]

7.6.14 TDCx_TIME2: Time 2 Register (address: 12h, CSBx asserted) [reset = 00_0000h]

7.6.15 TDCx_CLOCK_COUNT2: Clock Count Register (address: 13h, CSBx asserted) [reset = 00_0000h]

7.6.16 TDCx_TIME3: Time 3 Register (address: 14h, CSBx asserted) [reset = 00_0000h]

7.6.17 TDCx_CLOCK_COUNT3: Clock Count Registers (address: 15h, CSBx asserted) [reset = 00_0000h]

7.6.18 TDCx_TIME4: Time 4 Register (address: 16h, CSBx asserted) [reset = 00_0000h]

7.6.19 TDCx_CLOCK_COUNT4: Clock Count Register (address: 17h, CSBx asserted) [reset = 00_0000h]

7.6.20 TDCx_TIME5: Time 5 Register (address: 18h, CSBx asserted) [reset = 00_0000h]

7.6.21 TDCx_CLOCK_COUNT5: Clock Count Register (address: 19h, CSBx asserted) [reset = 00_0000h]

7.6.22 TDCx_TIME6: Time 6 Register (address: 1Ah, CSBx asserted) [reset = 00_0000h]

7.6.23 TDCx_CALIBRATION1: Calibration 1 Register (address: 1Bh, CSBx asserted) [reset = 00_0000h]

7.6.24 TDCx_CALIBRATION2: Calibration 2 Register (address: 1Ch, CSBx asserted) [reset = 00_0000h]