SWRU437B September 2015 – June 2020 WL1801MOD , WL1805MOD , WL1807MOD , WL1831MOD , WL1835MOD , WL1837MOD
3.2 Power Sequencing
The most crucial points during integration of the WiLink Module is that proper power-up and power-down sequences must be followed in order to avoid damage to the device.
1. On system level, either VBAT and VIO can come up first.
2. VBAT supplies, VIO supplies, and slow clock (SCLK) msut be enabled before EN is asserted and at all times when EN is active.
3. Keep a 60-µs delay between two consecutive device enables. The device is assumed to be in a shutdown state during that period; all enables to the device are low for that minimum duration.
4. Deassert the enable line at least 10 µs before the VBAT or VIO can be lowered. (The order in which supplies are turned off after EN shutdown in immaterial).
5. The SCLK I/O cell is a fail safe; the clock can be supplied before the VBAT and VIO supplies.
Figure 4. Power Sequencing