Pros: Included in DSP package (reduced board size and cost), On-chip POR voltage monitor and POWERGOOD holds RESET, ability to switch CVDD voltage by writing to LDOCNTL register
Cons: Better conversion power efficiency available with off-chip regulators (switching), LDOO cannot supply CVDDRTC - still need external [0.998 - 1.43] supply (or voltage divider/diode)
Before reset is released, LDOs ramp up to an untrimmed value. After reset is released, the bootloader trims the LDO outputs to their target voltage. Untrimmed voltages are screened to allow bootloader execution, but may be as low as 1 V. Take this into consideration if monitoring LDO output voltages before releasing reset. Consider asserting RESET for a fixed delay to allow for bandgap and LDOs to ramp to untrimmed values.
If not using DSP_LDOO to supply CVDD...
Warning: If DSP_LDOO does not supply CVDD (DSP_LDO_EN = HIGH), then no Power-On-Reset logic to hold RESET low internally while CVDD ramps
RESET must be held low externally until all power supplies are up and stable
Consider POWERGOOD signal timing and tolerance during CVDD ramp - when RESET released, CVDD must be > 0.998 V with margin