SNLU301 November 2021 SN75LVPE5412 , SN75LVPE5421
- Trademarks
- 1Introduction
-
2Description
- 2.1 Redriver-Mux 5-Level I/O Control Inputs
- 2.2 Redriver-Mux Modes of Operation
- 2.3 Redriver-Mux SMBus or I2C Register Control Interface
- 2.4 Redriver-Mux Equalization Control
- 2.5 Redriver-Mux RX Detect State Machine
- 2.6 Redriver-Mux DC Gain Control
- 2.7 DS320PR412-421EVM Global Controls
- 2.8 DS320PR412-421EVM Downstream Devices Control
- 2.9 DS320PR412-421EVM Upstream Devices Control
- 2.10 Quick-Start Guide (Pin Mode)
- 2.11 Quick-Start Guide (SMBus Slave Mode)
- 3Schematics
- 4PCB Layouts
- 5Bill of Materials
4 PCB Layouts
Figure 4-1 through Figure 4-6 illustrate the EVM PCB layout images.
Figure 4-1 Top Layer
Figure 4-2 Layer 2
Figure 4-3 Layer 3
Figure 4-4 Layer 4. 
Figure 4-5 Layer 5
Figure 4-6 Bottom Layer