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SLVUDE1 July 2025 TPS65219-Q1

4.3 Regulator Voltage Settings

This section describes how each of the PMIC power resources are configured.

Table 4-4 Buck Regulator Settings

PMIC Rail	Register Address	Field Name	Value	Description
Bucks Switching Mode (Global for all buck regulators)	0x03	BUCK_FF_ENABLE (Switching Mode)	0x0	Quasi-fixed frequency mode
Bucks Switching Mode (Global for all buck regulators)	0x03	BUCK_SS_ENABLE (Spread-Spectrum)	0x0	Spread spectrum disabled (only applicable if BUCK_FF_ENABLE=0x1)
BUCK1	0x0A	BUCK1_VSET (Output Voltage)	0xA	0.850V
	0x0A	BUCK1_UV_THR_SEL (UV threshold)	0x0	-5% UV detection
	0x0A	BUCK1_BW_SEL (Bandwidth)	0x1	high bandwidth
BUCK2	0x09	BUCK2_VSET (Output Voltage)	0x24	1.800V
	0x09	BUCK2_UV_THR_SEL (UV threshold)	0x0	-5% UV detection
	0x09	BUCK2_BW_SEL (Bandwidth)	0x1	high bandwidth
	0x03	BUCK2_PHASE_CONFIG	0x3	270 degrees (only applicable if BUCK_FF_ENABLE=0x1)
BUCK3	0x08	BUCK3_VSET (Output Voltage)	0x14	1.100V
	0x08	BUCK3_UV_THR_SEL (UV threshold)	0x0	-5% UV detection
	0x08	BUCK3_BW_SEL (Bandwidth)	0x1	high bandwidth
	0x03	BUCK3_PHASE_CONFIG	0x2	180 degrees (only applicable if BUCK_FF_ENABLE=0x1)

Note:

When bucks are configured for quasi-fixed frequency (BUCK_FF_ENABLE=0x0), changing the switching mode between auto-PFM and forced-PWM can be triggered by I2C (MODE_I2C_CTRL) or with one of the multi-function pins (MODE/RESET or MODE/STBY) if one of them is configured as MODE. Forced-PWM has priority over Auto-PFM.
BUCK2_PHASE_CONFIG, BUCK3_PHASE_CONFIG and BUCK_SS_ENABLE are only applicable when the buck regulators are configured for fixed frequency (BUCK_FF_ENABLE=0x1).

Table 4-5 LDO Regulator Settings

PMIC Rail	Setting	Register Address	Field Name	Value	Description
LDO1	output voltage	0x07	LDO1_VSET	0x36	3.300V
	Rail configuration	0x07	LDO1_LSW_CONFIG	0x0	Not Applicable (LDO1 not configured as load-switch)
	Rail configuration	0x07	LDO1_BYP_CONFIG	0x1	LDO1 configured as Bypass (only applicable if LDO1_LSW_CONFIG=0x0)
	UV threshold	0x1E	LDO1_UV_THR	0x0	-5% UV detection
LDO2	output voltage	0x06	LDO2_VSET	0x5	0.850V
	Rail configuration	0x06	LDO2_LSW_CONFIG	0x0	Not Applicable (LDO2 not configured as load-switch)
	Rail configuration	0x06	LDO2_BYP_CONFIG	0x0	LDO2 configured as LDO (only applicable if LDO2_LSW_CONFIG=0x0)
	UV threshold	0x1E	LDO2_UV_THR	0x0	-5% UV detection
LDO3	output voltage	0x05	LDO3_VSET	0x18	1.800V
	Rail configuration	0x05	LDO3_LSW_CONFIG	0x0	LDO Mode
	ramp configuration	0x05	LDO3_SLOW_PU_RAMP	0x1	Slow ramp for power-up (~3ms)
	UV threshold	0x1E	LDO3_UV_THR	0x0	-5% UV detection
LDO4	output voltage	0x04	LDO4_VSET	0x00	1.200V
	Rail configuration	0x04	LDO4_LSW_CONFIG	0x0	LDO Mode
	ramp configuration	0x04	LDO4_SLOW_PU_RAMP	0x1	Slow ramp for power-up (~3ms)
	UV threshold	0x1E	LDO4_UV_THR	0x0	-5% UV detection

Note:

If a LDO is configured in bypass-mode or LSW-mode, UV-detection is not supported.
If an LDO is configured in bypass-mode, the corresponding PVIN_LDOx supply must match the configured output voltage in the LDOx_VOUT register.
If LDO is configured as load-switch (LSW_mode), the desired voltage does not need to be configured in the LDOx_VOUT register.
In bypass- or LSW-mode, the LDO acts as a switch, where VOUT is VIN minus the drop over the FET-resistance.
If LDO1 or LDO2 is configured as bypass, it allows voltage and function changes between LDO (VOUT=1.8V) and VOUT=VSET register setting. This voltage/function change can be triggered by hardware (using the VSEL_SD pin when configured as SD) or by software (VSEL_SD_I2C_CTRL).