Figure 1-1 highlights the user interface items associated with the EVM. The VIN Power terminal block
(J1) is used for connection to the host input supply and the –VOUT Power terminal block (J4)
is used for connection to the load. These terminal blocks accept up to a 16-AWG wire.
Figure 1-1 EVM User Interface
Use the VIN S+ and VIN S– test points along with
the –VOUT Sense and GND Sense test points located near the power terminal blocks as
voltage monitoring points where voltmeters can be connected to measure VIN and –VOUT.
Do not use the monitoring test points as the input supply or output load connection
points. The PCB traces connecting to these test points are not designed to support
high currents.
Use the VIN scope test points (J2) and –VOUT
scope test points (J3) to monitor VIN and –VOUT waveforms with an oscilloscope. Use these
jumpers with the tip-and-barrel method. The two sockets of each test point are on 0.1-in
centers. Connect the scope probe tip to the upper socket pin labeled "?" and connect the
scope ground lead to the lower socket pin.
The control test points located near the bottom
and top left of the EVM test the features of the device. Refer to Table 2-1 for more information on the individual control test points.
The –VOUT Select jumper (J5) is provided to
select the desired negative output voltage:
–2.5 V
–3.3 V
–5 V
–12 V
–15 V
Before applying power to the EVM, make sure that the jumper is present and properly
positioned for the intended output voltage. Always remove input power before changing the
jumper settings.
The device can be turned on or off using the
system enable (SYS_EN) jumper (J6). Place the jumper in the ON position to enable the
device or in the OFF position to disable the device. If the jumper is left open, the EVM
will default to the OFF state. The undervoltage lockout (UVLO) can be set by populating
resistors R8 and R9 located on the bottom side of the EVM. If the ENABLE/UVLO feature is
not needed, remove resistor R9 from the board and place the jumper on the VIN_EN jumper
(J7).
The power good (PGOOD) test point is
available to monitor when a valid output voltage is present on the EVM. Additionally, the
PG_PU pin is present as a convenient point to connect a pullup voltage for the PGOOD
signal.
The frequency response test point (INJ)
along with the –VOUT Sense test point is available to inject a sinusoidal signal into the
system and measure the gain/phase response characteristics of the device.