SLVUBI2A July 2018 – October 2020 TPS650330-Q1 , TPS650331-Q1
The final silicon revision for the TPS65033x-Q1 family of PMICs is denoted B0. This corresponds to die revision PG 2.0. Table 11-1 lists the feature changes compared to the first revision of silicon, A0 or PG 1.0.
| Item | Design Block | Parameter Impacted | Silicon Revision A0 | Silicon Revision B0 | Details |
|---|---|---|---|---|---|
| 1 | BUCK1 | Output Voltage Settings | 3.0 V to 4.0 V | 2.5 V to 4.0 V | Maintains 50 mV increments |
| 2 | LDO | Output Voltage Settings | 2.7 V to 3.3 V | 1.8 V, 2.5 V to 3.3 V | 1.8 V and 1.825 V settings 2.5 V to 3.2 V settings in 25 mV increments 3.3 V setting |
| 3 | BUCK1 | PVIN_B1_UVLO | Rising threshold only | Rising and Falling thresholds | Same threshold settings as Rising thesholds with a 4% hysteresis delta betweein rising and falling |
| 4 | Digital | Warm Threshold | Exceeding Warm Threshold will keep State Machine from transitioning to the Active state | Option to allow the State Machine to transition to the Active State if the Warm Threshold is exceeded | User programmable in pre-production devices.Factory programmable in production devices. |
| 5 | Digital | LDO Pre-Bias Condition | Not applicable | Option to allow the LDO to power on into a pre-bias condition | User programmable in pre-production devices.Factory programmable in production devices. |
| 6 | Digital | I2C Bus | Always enabled | Option to disable | Factory programmable only |
| 7 | Digital | Configuration CRC | Can be disabled by the user during the configuration process | Can be disabled by the user during the configuration process and programmed to remain disabled | User programmable in pre-production devices.Factory programmable in production devices. |
| 8 | Digital | State Transition Control | Not applicable | Option to define the state transition for Priority 2 Faults (either the Reset State or Wait Power Cycle State) | User programmable in pre-production devices.Factory programmable in production devices.Does not apply to the TPS650331-Q1 device. |
| 9 | Digital | ABIST Run Time Control | ABIST only runs on power up | ABIST runs on power up or whenever commanded to run | Option is factory programmable only |
| 10 | Digital | SEQ Pin Latch | Not applicable | Option to latch the state of the SEQ pin in order to perform a complete power up or power down sequence | Option is factory programmable only |
| 11 | Digital | Power Good Status Register | Not applicable | Register bits added to provide the power good status of BUCK1, BUCK2, BUCK3, and the LDO. Status bits also added for nRSTOUT, GPIO, and SEQ pins | Read only register |