In this example, the TPS26631 variant is considered to highlight the current sharing during the 2 × pulse current support. For more information, see the Device Comparison Table in the TPS2663x 60-V, 6-A Power Limiting, Surge Protection Industrial eFuse data sheet for device selection. In a system where reverse current blocking is not required, the TPS1663 devices are recommended.

To limit the inrush current to 2.4 A (that is, 0.6 A per device), the R_{LIM_Low} is selected as 30 k?. Considering the cumulative current limit accuracy of 10% and to support maximum load current of 22 A, the current limit is set at 24 A (that is, 6 A per device). This results in 3.33-k? value for R_{LIM_High}.

The resistors R1, R2, and R3 are selected as 887 k?, 29.4 k?, and 34 k?, respectively, to set 18 V as undervoltage lockout and 33 V as overvoltage trip point.

Leave dVdT pins OPEN because the R_ILIM resistor switch network is considered in this design.

In parallel configuration, IMON pins of all the devices can be combined to monitor the total system current. The maximum value of the R_IMON resistor can be determined by Equation 1. The maximum V_IMON voltage is determined by the ADC input range and it is 3.3 V.

Where GAIN_IMON is 27.9 μA/A (typ) and I_{OUT_max} is 48 A because of 2 × overcurrent pulse support with the TPS26631.

Using Equation 1, we get R_IMON as 2.46 k?.

The output of these pins are used only from the primary eFuse to control downstream load and these pins are left OPEN for the rest of the parallel TPS26631 devices.

The TPS2663 device uses PGTH as the output load voltage monitor and to set the downstream loads UVLO threshold. The voltage at PGTH determines the way the TPS2663 recovers during the system faults. During the fault recovery instance, if the V_(PGTH) level is above V_(PGTHF), then the internal FET turns ON with a fast slew rate to meet Class-A system performance during surge events with optimal output buffer capacitance.

Typically, the minimum operating voltage of the DC-DC converter designed for 24-V rail is at 15 V. Assuming UVLO to be at 20% lower level, V_{UVLO_DC-DC} = 12 V. Use Equation 2 to calculate R₄ and R₅.

V_(PGTHF) = 1.14 V. Assuming R₅ = 56 k?, R₄ comes out to be approximately 499 k?.

During the surge event T_SURGE, the output capacitor C_OUT of the TPS2663 provides energy to the load. The C_OUT should be selected such that the output voltage does not drop below V_{UVLO_DC-DC} during T_SURGE interval. Use Equation 3 to compute the required buffer capacitor C_OUT:

where

• P_(DC-DC) = max load power ≈ 500 W
• T_SURGE ≈ 1 ms
• V_{(IN_SYS)} = 24 V
• V_{(UV_DC-DC)} = 15 V

The value is determined to be C_OUT = 2.85 mF. Choose a capacitor with ±10% tolerance, C_OUT = 3 mF / 35 V electrolytic capacitor.

A minimum of 0.1-μF ceramic decoupling capacitor is recommended at the input and the output for each of the eFuse.

Choose at least a 80-V rated N-channel FET. Two CSD19532Q5B FETs are used in parallel to support continuous load current of 22 A.

For clamping ±500-V, 2-Ω surge voltages with in the absolute maximum voltage rating of the TPS2663 device, bidirectional TVS diode SMCJ36CA is used at the input. Similarly, to clamp the negative voltages at the output during fast turn-off events, a Schottky diode B560C-13-F is recommended at the output.