SLUUCF9A March 2021 – April 2021 TPS566231 , TPS566238
5.1 Layout
The board layout for the TPS566231PEVM is shown in Figure 5-1 and Figure 5-2 to Figure 5-5.
TPS566231PEVM is with four layers, The top layer contains the main power traces for VIN, VOUT and GND. Also on the top layer are connections for the pins of the TPS566231P and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C1, C2, C3 and C4 are located as close to Vin pins and PGND pins of the IC as possible. The input and output connectors, test points and all of the components are located on the top side.
The bottom layer is a ground plane along with signal ground copper fill and the feed back trace from the point of regulation to the top of the resistor divider network.
Two inner layers are ground plane.
Figure 5-1 Top
Assembly
Figure 5-2 Top
Layer
Figure 5-3 Inner1
Layer
Figure 5-4 Inner2
Layer
Figure 5-5 Bottom
Layer