SLLA549 July 2021 TCAN4550 , TCAN4550-Q1 , TCAN4551-Q1
The dampening resistor Rd placed between the OSC1 pin of TCAN455x and the crystal along with the capacitor CL1 will help attenuate the Vpp level. The dampening series resistance Rd will limit the current and lower the voltage amplitude of the oscillation waveform by forming a voltage divider with the CL1 capacitor further reducing the power dissipated across the crystal and keeping the voltage on the OSC2 pin above the clock input detection threshold needed to prevent the Amplifier and Bias Control block from being disabled. The reactance of the CL1 capacitor can be calculated by following formula:
In a typical application using FR-4 PCB material contributing 2-3 pF of stray parasitic capacitance, and a crystal with an 8 pF load capacitance specification, this resistance Rd is typically in the range of 50 to 100 ohms and CL1 as low as 1 pF or 2.2 pF should be sufficient to ensure that OSC2 pin swings above the clock input detection threshold.
This dampening series resistance will be added to the load resistance seen by the oscillator and reduce the negative resistance margin. Recalculate the negative resistance margin with this additional series resistance to determine if there is still enough safety margin and that the magnitude of the negative resistance is still 3 to 5 times greater than the load resistance + Rs with the following formula:
Ensure that this does not exceed the negative resistance margin available. If the margin is too small, then the dampening series resistor may need to be reduced to a value that satisfies both the safety margin and drive level requirements. If this cannot be done, then larger load capacitors, a crystal with a lower motional resistance, and or a higher drive level specification must be used.