3.2.3 Serial-Peripheral Interface

The PGA450-Q1 device can also be put into a RESET state where the microcontroller is not active. During this state, SPI is the only digital interface that can be used. The low-side drivers can still be triggered to begin an ultrasonic burst and the analog front-end and digital data path can still store the returned echo signal in the FIFO RAM. However, any processing of the FIFO RAM by the internal microprocessor to determine the location of an object does not occur. The FIFO RAM data can be read over SPI, allowing an external microprocessor to process the data.

To provide a quick evaluation of the performance of the PGA450-Q1 device using the PGA450Q1EVM-S and GUI without having to develop sophisticated 8051 μP software, the GUI provides an intuitive interface tab, the Evaluation Tab, that collects all required information regarding the transducer drive and receive. For the transducer drive, it includes: transducer frequency; transducer drive voltage, VREG; transformer configuration; and number of drive pulses. For the transducer signal receive, it includes signal-processing parameters: LNA gain setting; BPF and LPF coefficient; clock selection; FIFO mode; and FIFO downsample size.