SLAZ102AB October 2012 – May 2021 CC430F6137
PORT Module
Functional
Certain pins when subject to negative high current pulses may cause latch-up in adjacent pins.
Pins subject to negative high current pulses may cause latch-up in adjacent pins. The latch-up condition exists only if the adjacent pin configurations also referred to as 'affected-pin' configuration are one of the following:
(1) GPIO input driven high by an external source
(2) GPIO output driven high with Full Drive strength OR Reduced Drive strength settings
(3) Peripheral configuration where the peripheral drives pin high or causes pin to be driven high externally
The following affected-pin configurations will not sustain latch-up:
(1) GPIO input driven low
(2) GPIO output driven low
(3) Peripheral configuration where the peripheral drives pin low or causes pin to be driven low externally
(4) Peripheral configuration as LCD pin
Note that for affected-pin configurations with LCD functionality, the window of latch-up when the pin is driven being high still exists but is of extremely short duration and hence there is a low probability of latch-up occurrence.
All affected pins must be driven low when not in use. If the affected pins are not driven low, then connecting a series resistor of 330 ohms to limit the latch-up current is recommended.
For more details on trigger currents, affected pin configurations and workarounds refer to the document
PORT17 Guidance SLAA563