SFFS478 February 2024 LM74502-Q1 , LM74502H-Q1
This section provides a Failure Mode Analysis (FMA) for the pins of the LM74502-Q1, LM74502H-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the LM74502-Q1, LM74502H-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM74502-Q1, LM74502H-Q1 data sheet.
The pin FMA is provided under the assumption that the device is operating under the specified ranges within the Recommended Operating Conditions section of the data sheet.
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN/UVLO | 1 | Device will not power up and will be in shutdown mode. | B |
| GND | 2 | No effect on device behavior. | D |
| N.C | 3 | No effect on the device behavior. | D |
| VCAP | 4 | Device may heat up and damage due to increased quiescent current. | A |
| VS | 5 | Device will not power up. This is equivalent to input supply shorted to ground. | B |
| GATE | 6 | External MOSFET will not turn on. Device may heat up and damage due to increased quiescent current. | A |
| OV | 7 | Overvoltage functionality will not be available. | B |
| SRC | 8 | Device quiescent current may increase. Based on input voltage, external MOSFET may sustain damage due to GATE to SOURCE maximum voltage specification violation. | B |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN/UVLO | 1 | Device will not power up and will be in shutdown mode due to internal pull down on EN/UVLO pin. | B |
| GND | 2 | Device will not power up. | B |
| N.C | 5 | No effect on the device behavior. | D |
| VCAP | 4 | Charge pump will not come up. External FET will be off. | B |
| VS | 5 | Device will not power up. This is equivalent to input supply not available. | B |
| GATE | 6 | External FET will not turn on. | B |
| OV | 7 | Overvoltage functionality will not be available. | B |
| SRC | 8 | Device will not be able to turn off external FETs completely. System will not have any protection from input reverse polarity after external FETs are turned on. | B |
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| EN/UVLO | 1 | GND | Device will not power up and will be in shutdown mode. | B |
| GND | 2 | N.C | No effect on the device performance. | D |
| N.C | 3 | VCAP | No effect on the device performance. | D |
| VCAP | 4 | - | VCAP is the corner pin. No effect on the device performance. | D |
| VS | 5 | GATE | External FET will not turn on. Device quiescent current may increase. | B |
| GATE | 6 | OV | Device GATE drive will be turned off due to OV comparator trigger. | B |
| OV | 7 | SRC | Device GATE drive will be turned off due to OV comparator trigger. Device GATE pin may oscillate between on and off state. | B |
| SRC | 8 | - | SRC is the corner pin. No effect on the device performance. | D |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| EN/UVLO | 1 | Device will always be on. | B |
| GND | 2 | Device will not power up. It is equivalent to input supply short condition. | B |
| N.C | 3 | No effect on the device performance. | D |
| VCAP | 4 | Device charge pump will not come up. External FET will be off. | B |
| VS | 5 | No effect on the device performance. | D |
| GATE | 6 | External FET will be off. | B |
| OV | 7 | Device will be off due to OV comparator trigger. | B |
| SRC | 8 | Device will not be able to disconnect the load from supply due to input supply to SRC pin shorting. | B |