B Forbidden States of the Johnson Counter

Johnson counters have a subtle but potentially troublesome issue of unused states. A Johnson counter containing N flip-flops is a state machine having 2^N unique states of which only 2 × N are used, leaving 2^N – 2 × N unused. For an 8-bit register, that amounts to 240 unused states– the vast majority. If the Johnson counter somehow gets out of the desired cycle due to a glitch (cosmic ray, power supply noise, bad start-up conditions, and so forth) additional logic is required for recovery; otherwise the counter remains forever locked out of the desired cycle, only clocking through unused states and producing bad output. The additional octal input NAND gate and one-shot timer shown in Figure B-1 demonstrate one relatively easy way using common parts to detect and correct this fault condition within a few output cycles. As a side benefit, during normal operation the octal NAND gate generates a falling edge coinciding with 0° of the cosine function. This sync pulse extends the output of the ‘123 one-shot indefinitely so long as the Johnson counter is operating correctly. If the sync pulse goes missing beyond the timeout of the one-shot, the output goes low and 1s are clocked into the shift register via the 2-input NAND until the circuit is reset back to the correct pattern.

The new HCS series of MSI logic gates feature Schmitt triggers on all inputs, including _CLR. This allows for easy RC power-on reset as shown in Figure B-1. The inline resistor on the _CLR signal limits the current from the reset capacitor through the ESD structures of the logic gate when VDD is powered down quickly.