ZHCSFJ6B August 2016 – March 2022 UCD9090A
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1 Power Supply Sequencing
- 7.4.2 Pin-Selected Rail States
- 7.4.3 Monitoring
- 7.4.4 Fault Responses and Alert Processing
- 7.4.5 Shut Down All Rails and Sequence On (Resequence)
- 7.4.6 GPIOs
- 7.4.7 GPO Control
- 7.4.8 GPO Dependencies
- 7.4.9 GPI Special Functions
- 7.4.10 Power Supply Enables
- 7.4.11 Cascading Multiple Devices
- 7.4.12 PWM Outputs
- 7.4.13 Programmable Multiphase PWMs
- 7.4.14 Margining
- 7.4.15 Run Time Clock
- 7.4.16 System Reset Signal
- 7.4.17 Watch Dog Timer
- 7.4.18 Data and Error Logging to Flash Memory
- 7.4.19 Brownout Function
- 7.4.20 PMBus Address Selection
- 7.4.21 Device Reset
- 7.4.22 JTAG Interface
- 7.4.23 Internal Fault Management and Memory Error Correction (ECC)
- 7.5 Programming
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- RGZ|48
散熱焊盤機械數據 (封裝 | 引腳)
- RGZ|48
訂購信息
7.4.9 GPI Special Functions
Special input functions for which GPIs can be used. There can be no more than one pin assigned to each of these functions.
- GPI Fault Enable - When set, the de-assertion of the GPI is treated as a fault.
- Latched Statuses Clear Source - When a GPO uses a latched status type (_LATCH), a correctly configured GPI clears the latched status.
- Input Source for Margin Enable - When this pin is asserted, all rails with margining enabled will be put in a margined state (low or high).
- Input Source for Margin Low/Not-High - When this pin is asserted all margined rails will be set to Margin Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails will be set to Margin High.
- Fault Shutdown Rails - See Section 7.4.9.1.
- Configured as Sequencing Debug Pin - See Section 7.4.9.2.
- Configured as Fault Pin - See Section 7.4.9.2.
- Enable Cold Boot Mode - See Section 7.4.9.4.
The polarity of GPI pins can be configured to be either Active Low or Active High. The first 3 GPIs that are defined regardless of their main purpose will be used for the PIN_SELECTED_RAIL_STATES command.
Figure 7-17 GPI Configurations