ZHCSFJ6B August 2016 – March 2022 UCD9090A
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
The UCD9090A has an integrated power-on reset (POR) circuit which monitors the supply voltage. At power up, the POR detects the V33D rise. When V33D is less than VRESET, the device comes out of reset.
The device can be forced into the reset state by an external circuit connected to the RESET pin. A logic low voltage on this pin for longer than tRESET holds the device in reset. it comes out of reset within 1 ms after RESET is released, and can return to a logic-high level. To avoid an erroneous trigger caused by noise, connect RESET to a 10-kΩ pullup resistor (from RESET to 3.3 V) and 1000-pF capacitor (from RESET to AVSS).
Any time the device comes out of reset, it begins an initialization routine that lasts about 20 ms. During the Initialization routine, the FPWM pins are held low. and all other GPIO and GPI pins are open-circuit. At the end of initialization, the device begins normal operation as defined by the device configuration.