ZHCSFJ6B August 2016 – March 2022 UCD9090A
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1 Power Supply Sequencing
- 7.4.2 Pin-Selected Rail States
- 7.4.3 Monitoring
- 7.4.4 Fault Responses and Alert Processing
- 7.4.5 Shut Down All Rails and Sequence On (Resequence)
- 7.4.6 GPIOs
- 7.4.7 GPO Control
- 7.4.8 GPO Dependencies
- 7.4.9 GPI Special Functions
- 7.4.10 Power Supply Enables
- 7.4.11 Cascading Multiple Devices
- 7.4.12 PWM Outputs
- 7.4.13 Programmable Multiphase PWMs
- 7.4.14 Margining
- 7.4.15 Run Time Clock
- 7.4.16 System Reset Signal
- 7.4.17 Watch Dog Timer
- 7.4.18 Data and Error Logging to Flash Memory
- 7.4.19 Brownout Function
- 7.4.20 PMBus Address Selection
- 7.4.21 Device Reset
- 7.4.22 JTAG Interface
- 7.4.23 Internal Fault Management and Memory Error Correction (ECC)
- 7.5 Programming
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購(gòu)信息
5 Pin Configuration and Functions
Note:
The number of configurable rails is a maximum of ten. The maximum number of configurable GPIs is eight. The maximum number of configurable boolean logic GPOs is ten.
Figure 5-1 Pin Assignments for the VQFN PackageFigure 5-2 RGZ Package, 48-Pin VQFN With Exposed Thermal
Pad (Top View)
Table 5-1 Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ANALOG MONITOR INPUTS | |||
| MON1 | 1 | I | Analog input (0 V–2.5 V) |
| MON2 | 2 | I | Analog input (0 V–2.5 V) |
| MON3 | 38 | I | Analog input (0 V–2.5 V) |
| MON4 | 39 | I | Analog input (0 V–2.5 V) |
| MON5 | 40 | I | Analog input (0 V–2.5 V) |
| MON6 | 41 | I | Analog input (0 V–2.5 V) |
| MON7 | 42 | I | Analog input (0 V–2.5 V) |
| MON8 | 45 | I | Analog input (0 V–2.5 V) |
| MON9 | 46 | I | Analog input (0 V–2.5 V) |
| MON10 | 48 | I | Analog input (0 V–2.5 V) |
| MON11 | 37 | I | Analog input (0.2 V–2.5 V) |
| GPIO | |||
| GPIO1 | 4 | I/O | General-purpose discrete I/O |
| GPIO2 | 5 | I/O | General-purpose discrete I/O |
| GPIO3 | 6 | I/O | General-purpose discrete I/O |
| GPIO4 | 7 | I/O | General-purpose discrete I/O |
| GPIO13 | 18 | I/O | General-purpose discrete I/O |
| GPIO14 | 21 | I/O | General-purpose discrete I/O |
| GPIO15 | 24 | I/O | General-purpose discrete I/O |
| GPIO16 | 25 | I/O | General-purpose discrete I/O |
| GPIO17 | 26 | I/O | General-purpose discrete I/O |
| PWM OUTPUTS | |||
| FPWM1/GPIO5 | 10 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
| FPWM2/GPIO6 | 11 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
| FPWM3/GPIO7 | 12 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
| FPWM4/GPIO8 | 13 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
| FPWM5/GPIO9 | 14 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
| FPWM6/GPIO10 | 15 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
| FPWM7/GPIO11 | 16 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
| FPWM8/GPIO12 | 17 | I/O/PWM | PWM (15.259 kHz to 125 MHz) or GPIO |
| PWM1/GPI1 | 22 | I/PWM | PWM (0.93 Hz to 7.8125 MHz) or GPI |
| PWM2/GPI2 | 23 | I/PWM | PWM (0.93 Hz to 7.8125 MHz) or GPI |
| PMBus COMM INTERFACE | |||
| PMBus_CLK | 8 | I/O | PMBus clock (must have pullup to 3.3 V) |
| PMBus_DATA | 9 | I/O | PMBus data (must have pullup to 3.3 V) |
| PMBus_ALERT | 19 | O | PMBus alert, active-low, open-drain output (must have pullup to 3.3 V) |
| PMBus_CNTRL | 20 | I | PMBus control |
| PMBus_ADDR0 | 44 | I | PMBus analog address input. Least-significant address bit |
| PMBus_ADDR1 | 43 | I | PMBus analog address input. Most-significant address bit |
| JTAG | |||
| TCK/GPIO18 | 27 | I/O | Test clock or GPIO |
| TDO/GPIO19 | 28 | I/O | Test data out or GPIO |
| TDI/GPIO20 | 29 | I/O | Test data in (tie to Vdd with 10-kΩ resistor) or GPIO |
| TMS/GPIO21 | 30 | I/O | Test mode select (tie to Vdd with 10-kΩ resistor) or GPIO |
| TRST | 31 | I | Test reset – tie to ground with 10-kΩ resistor |
| INPUT POWER AND GROUNDS | |||
| RESET | 3 | — | Active-low device reset input. Hold low for at least 2 μs to reset the device. |
| V33A | 34 | — | Analog 3.3-V supply. Refer to the Section 10.1 section. |
| V33D | 33 | — | Digital core 3.3-V supply. Refer to the Section 10.1 section. |
| BPCap | 35 | — | 1.8-V bypass capacitor. Refer to the Section 10.1 section. |
| AVSS1 | 36 | — | Analog ground |
| AVSS2 | 47 | — | Analog ground |
| DVSS | 32 | — | Digital ground |
| Thermal pad | — | QFN ground pad. Tie to ground plane. | |