ZHCSJQ1D November 2010 – April 2019 UCD90160
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1 Power-Supply Sequencing
- 7.4.2 Pin-Selected Rail States
- 7.4.3 Voltage Monitoring
- 7.4.4 Fault Responses and Alert Processing
- 7.4.5 Shut Down All Rails and Sequence On (Resequence)
- 7.4.6 GPIOs
- 7.4.7 GPO Control
- 7.4.8 GPO Dependencies
- 7.4.9 GPI Special Functions
- 7.4.10 Power-Supply Enables
- 7.4.11 Cascading Multiple Devices
- 7.4.12 PWM Outputs
- 7.4.13 Programmable Multiphase PWMs
- 7.4.14 Margining
- 7.4.15 System Reset Signal
- 7.4.16 Watch Dog Timer
- 7.4.17 Run Time Clock
- 7.4.18 Data and Error Logging to Flash Memory
- 7.4.19 Brownout Function
- 7.4.20 PMBus Address Selection
- 7.5 Programming
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.15 System Reset Signal
The UCD90160 can generate a programmable system-reset pulse as part of sequence-on. The pulse is created by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration can be programmed as shown in Table 6. See an example of two SYSTEM RESET signals Figure 22. The first SYSTEM RESET signal is configured so that it de-asserts on Power Good On and it asserts on Power Good Off after a given common delay time. The second SYSTEM RESET signal is configured so that it sends a pulse after a delay time once Power Good On is achieved. The pulse width can be configured between 0.001s to 32.256s. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for pulse width configuration details.
Figure 22. System Reset with and without Pulse Setting The system reset can react to watchdog timing. In Figure 23 The first delay on SYSTEM RESET is for the initial reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog is configured with a Start Time and a Reset Time. If these times expire without the WDI clearing them then it is expected that the CPU providing the watchdog signal is not operating. The SYSTEM RESET is toggled either using a Delay or GPI Tracking Release Delay to see if the CPU recovers.
Figure 23. System Reset with Watchdog Table 6. System-Reset Delay
| Delay |
|---|
| 0 ms |
| 1 ms |
| 2 ms |
| 4 ms |
| 8 ms |
| 16 ms |
| 32 ms |
| 64 ms |
| 128 ms |
| 256 ms |
| 512 ms |
| 1.02 s |
| 2.05 s |
| 4.10 s |
| 8.19 s |
| 16.38 s |
| 32.8 s |