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SLUSC99A July 2016 – January 2017 UCD3138128A

PRODUCTION DATA.

封裝選項

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PFC|80
- MTQF009B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		VALUE		UNIT
		MIN	MAX
Voltage	V33D to DGND	–0.3	3.8	V
	V33DIO to DGND	–0.3	3.8	V
	V33A to AGND	–0.3	3.8	V
	BP18 to DGND	-0.3	2.5	V
	Ground difference, \|DGND – AGND\|		0.3	V
	Voltage applied to any pin, excluding AGND⁽²⁾	–0.3	3.8	V
Junction Temperature, T_J		–40	125	°C
Storage temperature range, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Referenced to DGND

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
Digital power	V33D	3.0	3.3	3.6	V
Digital I/O power	V33DIO	3	3.3	3.6	V
Analog power	V33A	3	3.3	3.6	V
Digital power	BP18	1.6	1.8	2	V
Junction temperature, T_J		–40		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TQFP (QFN)	UNIT
THERMAL METRIC⁽¹⁾		80-PIN	UNIT
R_θJA	Junction-to-ambient thermal resistance	47.8	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	7.8
R_θJB	Junction-to-board thermal resistance	24.4
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	24.0
R_θJCbot	Junction-to-case (bottom) thermal resistance	N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, .

7.5 Electrical Characteristics

V33A = V33D = V33DIO = 3 V to 3.6 V; 1 μF from BP18 to DGND, T_J = –40°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
	I33A⁽⁵⁾	Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled		7.5		mA
	I33DIO⁽⁵⁾	All GPIO and communication pins are open		0.35		mA
	I33D⁽⁵⁾	ROM program execution		69		mA
	I33	The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded.		90	100	mA
ERROR ADC INPUTS EAP, EAN
	EAP – AGND⁽⁵⁾		–0.15		1.998	V
	EAP – EAN⁽⁵⁾		–0.256		1.848	V
	Typical error range⁽⁵⁾	AFE = 0	–256		248	mV
	EAP – EAN Error voltage digital resolution	AFE = 3	0.8	1	1.25	mV
		AFE = 2	1.7	2	2.4	mV
		AFE = 1	3.55	4	4.5	mV
		AFE = 0	6.90	8	9.10	mV
R_EA	Input impedance⁽⁵⁾ (See Figure 11)	AGND reference	0.5			MΩ
I_OFFSET	Input offset current⁽⁵⁾ (See Figure 11)	EADC is in idle state	–5		5	μA
	EADC Offset	Input voltage = 0 V at AFE = 0	–20		20	mV
		Input voltage = 0 V at AFE = 1	–10		10	mV
		Input voltage = 0 V at AFE = 2	–6		6	mV
		Input voltage = 0 V at AFE = 3	–4		4	mV
	Sample Rate⁽⁵⁾				15.625	MHz
	Analog Front End Amplifier Bandwidth⁽⁵⁾			100		MHz
A₀	Gain⁽⁵⁾	See Figure 12		1		V/V
A₀	Minimum output voltage				25	mV
EADC DAC
	DAC range		0		1.6	V
	VREF DAC reference resolution	10 bit, No dithering enabled		1.56		mV
	VREF DAC reference resolution⁽⁵⁾	With 4 bit dithering enabled		97.6		μV
	INL	Ensured INL	–1.5		1.5	LSB
	INL	Typical INL (T_J =25°C, V33A = V33D = V33DIO = 3.3 V)		–0.4/+0.7		LSB
	DNL	Guaranteed DNL	–2.0		1	LSB
	DNL	Typical DNL (T_J = 25°C, V33A = V33D = V33DIO = 3.3 V)		–0.4/+0.3		LSB
	DAC reference voltage		1.58		1.61	V
ADC12
I_BIAS	Bias current for PMBus address pins		9.5		10.5	μA
	Measurement range for voltage monitoring		0		2.5	V
	Internal ADC reference voltage		2.475	2.500	2.525	V
	Change in Internal ADC reference from 25°C reference voltage⁽⁵⁾	25°C to –40°C		–2.36		mV
		25°C to 125°C		–5.45		mV
	ADC12 INL integral nonlinearity, end point⁽⁵⁾	ADC_SAMPLING_SEL = 0 or 7 for all ADC12 data	–3.9	–2.5/2.2	4.5	LSB
	ADC12 INL integral nonlinearity, best fit line⁽⁵⁾		–2.4	–1.6/1.7	2.9	LSB
	ADC12 DNL differential nonlinearity⁽⁵⁾		–1.0	–0.6/+2.6	3.8	LSB
	ADC Zero Scale Error		–5		5	mV
	ADC Full Scale Error		–30		30	mV
	Input bias	2.5 V applied to pin			200	nA
	Input leakage resistance⁽⁵⁾	ADC_SAMPLING_SEL = 0		2		MΩ
	Input leakage resistance⁽⁵⁾	ADC_SAMPLING_SEL = 7		1		MΩ
	Input Capacitance⁽⁵⁾			10		pF
DIGITAL INPUTS/OUTPUTS⁽²⁾
V_OL	Low-level output voltage⁽³⁾⁽¹⁾	I_OH = 4 mA, V33DIO = 3 V			DGND + 0.25	V
V_OH	High-level output voltage ⁽³⁾	I_OH = –4 mA, V33DIO = 3 V	V33DIO – 0.6			V
V_IH	High-level input voltage	V33DIO = 3 V	2.1			V
V_IL	Low-level input voltage	V33DIO = 3 V			1.1	V
I_OH	Output sinking current				4	mA
I_OL	Output sourcing current		–4			mA
SYSTEM PERFORMANCE
I_SHARE	Current share current source (See Figure 34)		238		259	μA
R_SHARE	Current share resistor (See Figure 34)		9.6		10.4	kΩ
POWER ON RESET AND BROWN OUT (V33A PIN)
VGH	Voltage good High	See Figure 9	2.302	2.53	2.836	V
VGL	Voltage good Low		2.248	2.48	2.781	V
V_res	Voltage at which IReset signal is valid⁽⁵⁾		0.8			V
	Brownout	Internal signal warning of brownout conditions	2.774	2.9	3.077	V
TEMPERATURE SENSOR
V_TEMP	Voltage range of sensor⁽⁵⁾		1.46		2.44	V
	Voltage resolution⁽⁵⁾	Volts/°C		6.3		mV/ºC
	Temperature resolution⁽⁵⁾	Degree C per bit		0.0969		ºC/LSB
	Accuracy⁽⁵⁾⁽⁶⁾	–40°C to 125°C	–10	±5	10	ºC
	Temperature range⁽⁵⁾	–40°C to 125°C	–40		125	ºC
I_TEMP	Current draw of sensor when active⁽⁵⁾			30		μA
V_AMB	Ambient temperature	Trimmed 25°C reading	1.858	1.9	1.954	V
ANALOG COMPARATOR
DAC	Reference DAC Range⁽⁵⁾		0.019		2.5	V
	Reference voltage		2.478	2.5	2.513	V
	Bits			7		bits
	INL⁽⁵⁾		–0.5		0.21	LSB
	DNL⁽⁵⁾		0.06		0.12	LSB
	Offset		–5.5		19.5	mV
	Reference DAC buffered output load⁽⁷⁾		–0.5		1	mA
	Buffer offset (–0.5 mA)	0.156 V < DAC < 2.363 V	–10		10	mV
	Buffer offset (1.0 mA)	0.059 V < DAC < 2.305 V	–10		10	mV
RTC INTERFACE
f_RTC	RTC external input frequency ⁽⁸⁾			10		MHz

(1) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.

(2) On the 40 pin package V33DIO is connected to V33D internally.

(3) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at V_OL; maximum source current per pin = 6 mA at V_OH.

(4) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.

(5) Characterized by design and not production tested.

(6) Ambient temperature offset value from the TEMPSENCTRL register should be used to meet accuracy.

(7) Available from reference DACs for comparators D, E, F and G.

(8) Performance dependent on selected external components. The maximum frequency should be no more than 12 MHz.

7.6 Timing Characteristics

V33A = V33D = V33DIO = 3.0 V to 3.6 V; 1 μF from BP18 to DGND, T_J = –40°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
EADC DAC
t	Settling Time⁽¹⁾	From 10% to 90%		250		ns
ADC12
	ADC single sample conversion time⁽¹⁾	ADC_SAMPLING_SEL= 0		3.9		μs
	ADC single sample conversion time⁽¹⁾	ADC_SAMPLING_SEL= 7		1..9		μs
SYSTEM PERFORMANCE
	Processor master clock (MCLK)			31.25		MHz
t_Delay	Digital filter delay⁽⁴⁾				6	MCLKs
f_(PCLK)	Internal oscillator frequency	–40°C to +125°C	240	250	260	MHz
f_(PCLK)	Internal oscillator frequency	–5°C to +85°C	245	250	255	MHz
TWD	Watchdog time out range⁽¹⁾	Total time is: TWD x (WDCTRL.PERIOD+1)	12.02	13.08	13.65	ms
	Time to disable DPWM output based on active FAULT pin signal⁽¹⁾	High level on FAULT pin		80		ns
	Flash Read			1		MCLKs
	Retention period of flash content (data retention and program)	T_J= 25°C	100			years
	Program time to erase one page or block in data flash or program flash			20		ms
	Program time to write one word in program flash			50		µs
	Program time to write one word in data flash			40		µs
	Sync-in/sync-out pulse width⁽¹⁾	Sync pin		256		ns
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 9)
t_POR⁽¹⁾		Time delay after power is good or RESET* relinquished		1		ms
t_EXC1	The time it takes from the device to exit a reset state and begin executing the boot flash.⁽¹⁾	I_RESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state.		0.5		ms
t_EXC2	The time it takes from the device to exit a reset state and begin executing program flash bank 0 (32 kB).⁽¹⁾	I_RESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state.		3		ms
t_EXCT	The time it takes from the device to exit a reset state and begin executing the total program flash (64 kB).⁽¹⁾	I_RESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state.		6		ms
TEMPERATURE SENSOR⁽¹⁾
t_ON⁽¹⁾		Turn on time / settling time of sensor		100		μs
ANALOG COMPARATOR
	Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator.⁽¹⁾			90	150	ns

(1) Characterized by design and not production tested.

7.7 PMBus/SMBus/I²C Timing

The timing characteristics and timing diagram for the communications interface that supports I²C, SMBus, and PMBus in Slave or Master mode are shown in PMBus/SMBus/I2C Timing, Figure 6, and Figure 7. The numbers in PMBus/SMBus/I2C Timing shows that the device supports standard (100 kHz), fast (400 kHz), and fast-mode plus (1 MHz) speeds. ⁽¹⁾

PARAMETER		TEST CONDITIONS	100 kHz Class		400 kHz Class		1 MHz Class⁽²⁾		UNIT
PARAMETER		TEST CONDITIONS	MIN	MAX	MIN	MAX	MIN	MAX	UNIT
Typical values at T_A = 25 °C and VCC = 3.3 V (unless otherwise noted)
f_SMB	SMBus/PMBus operating frequency	Slave mode, SMBC 50% duty cycle	10	100	10	400	10	1000	kHz
f_I2C	I²C operating frequency	Slave mode, SCL 50% duty cycle	10	100	10	400	10	1000	kHz
t_(BUF)	Bus free time between start and stop		4.7		1.3		0.5		µs
t_(HD:STA)	Hold time after (repeated) start		4		0.6		0.26		µs
t_(SU:STA)	Repeated start setup time		4.7		0.6		0.26		µs
t_(SU:STO)	Stop setup time		4		0.6		0.26		µs
t_(HD:DAT)	Data hold time	Receive mode	0		0		0		ns
t_(SU:DAT)	Data setup time		250		100		50		ns
t_(TIMEOUT)	Error signal/detect		25	35	25	35	25	35	ms
t_(LOW)	Clock low period		4.7		1.3		0.5		µs
t_(HIGH)	Clock high period		4	50	0.6	50	0.26	50	µs
t_(LOW:SEXT)	Cumulative clock low slave extend time			25		25		25	ms
t_r	Clock/data fall time	Rise time t_r = (V_ILmax – 0.15) to (V_IHmin + 0.15)	20 + 0.1 Cb	300	20 + 0.1 Cb	300	20 + 0.1 Cb	120	ns
t_f	Clock/data rise time	Fall time t_f = 0.9 VDD to (V_ILmax – 0.15)	20 + 0.1 Cb	1000	20 + 0.1 Cb	300	20 + 0.1 Cb	120	ns
C_b	Total capacitance of one bus line					400			pF