SLUSC99A July 2016 – January 2017 UCD3138128A
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parametric Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 System Module
- 9.3.2 Peripherals
- 9.3.3 Automatic Mode Switching
- 9.3.4 DPWMC, Edge Generation, Intramux
- 9.3.5 Synchronous Rectifier MOSFET Ramp And IDE Calculation
- 9.3.6 Filter
- 9.3.7 Communication Ports
- 9.3.8 Real Time Clock
- 9.3.9 External Crystal Interface
- 9.3.10 Timers
- 9.3.11 General Purpose ADC12
- 9.3.12 Miscellaneous Analog
- 9.3.13 Brownout
- 9.3.14 Global I/O
- 9.3.15 Temperature Sensor Control
- 9.3.16 I/O Mux Control
- 9.3.17 Current Sharing Control
- 9.3.18 Temperature Reference
- 9.4 Device Functional Modes
- 9.5 Register Maps
- 10Applications and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
8 Parametric Measurement Information
Figure 8. Best Fit INL and End Point INL
Figure 9. Power On Reset (POR) / Brown Out Reset (BOR)
| VGH – | This is the V33A threshold where the internal power is declared good. The UCD3138xA comes out of reset when above this threshold. | |||
| VGL – | This is the V33A threshold where the internal power is declared bad. The device goes into reset when below this threshold. | |||
| Vres – | This is the V33A threshold where the internal reset signal is no longer valid. Below this threshold the device is in an indeterminate state. | |||
| IReset – | This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding the reset pin on the IC low. | |||
| tPOR – | The time delay from when VGH is exceeded to when the device comes out of reset. | |||
| Brown Out – | This is the V33A voltage threshold at which the device sets the brown out status bit. In addition an interrupt can be triggered if enabled. | |||
8.1 Typical Clock Gating Power Savings
The CLKGATECTRL register provides control bits that can enable or disable the clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.
By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current consumption of the device. The power savings chart displays the power savings per module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.