ZHCSRA0 December 2022 UCC5871-Q1
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| fSPI | SPI clock frequency(1) | 4 | MHz | ||
| tCLK | SPI clock period(1) | 250 | ns | ||
| tCLKH | CLK logic high duration(1) | 90 | ns | ||
| tCLKL | CLK logic low duration(1) | 90 | ns | ||
| tSU_NCS | time between falling edge of nCS and rising edge of CLK(1) | 50 | ns | ||
| tSU_SDI | setup time of SDI before the falling edge of CLK(1) | 30 | ns | ||
| tHD_SDI | SDI data hold time (1) | 45 | ns | ||
| tD_SDO | time delay from rising edge of CLK to data valid at SDO(2) | 60 | ns | ||
| tHD_SDO | SDO output hold time(1) | 40 | ns | ||
| tHD_NCS | time between the falling edge of CLK and rising edge of nCS(1) | 50 | ns | ||
| tHI_NCS | SPI transfer inactive time(1) | 250 | ns | ||
| tACC | nCS low to SDO out of high impedance(2) | 60 | 80 | ns | |
| tDIS | time between rising edge of nCS and SDO in tri-state(2) | 30 | 50 | ns | |