ZHCSQ75C June 2022 – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
- 9.2.2.2 Primary Magnetizing Inductance of the Flyback Transformer (LM)
- 9.2.2.3 Number of Turns of the Flyback Transformer Windings
- 9.2.2.4 Current Sense Resistors (R24, R25) and Current Limiting
- 9.2.2.5 Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
- 9.2.2.6 Primary-Side Current Stress and Input Capacitor Selection
- 9.2.2.7 Secondary-Side Current Stress and Output Capacitor Selection
- 9.2.2.8 VDD Capacitors (C12, C18)
- 9.2.2.9 Gate Drive Network (R14, R16, Q6)
- 9.2.2.10 VREF Capacitor (C18)
- 9.2.2.11 RT/CT Components (R12, C15)
- 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
- 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
- 9.2.2.14 Voltage Feedback Compensation
- 9.2.3 Application Curves
- 9.3 PCB Layout Recommendations
- 9.4 Power Supply Recommendations
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- D|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
High-voltage and fast switching leads to a high dv/dt switching node, which generates a fair amount of noise. During PCB layout, the switching node must be kept away from quiet areas, such as the current sense circuitry, voltage feedback circuitry, and loop compensation components to reduce noise coupling.
It’s common knowledge that each time the MOSFET turns on a spike appears on the current sense resistor for a very short time. This spike can cause the MOSFET to turn off early if precautions are not taken. Figure 9 shows several important sub-circuits required for reliable operation. First, and most important, R21 and C22 form a low pass filter between the (noisy) RSENSE node and the CS pin. The low pass filter can attenuate most of the noise spike but too much filtering will delay the current information too. Second, Q6 and the components connected to its base are leading-edge blanking. This AC-coupled transistor pulls down on the CS voltage each time the MOSFET is turned on. The amount of leading-edge blanking is determined by C23, R26, and R27.
At duty cycles above 50 %, current mode control has a subharmonic oscillation phenomenon unless slope compensation is added. In Figure 9, R22 injects a small amount of voltage ramp to the CS pin. The voltage ramp for slope compensation is formed by passing the RT/CT voltage through an emitter-follower formed by Q7 and R23. The emitter follower buffers the RT/CT circuit so the switching frequency will not be changed. C21 ac-couples the output of the emitter follower to the CS pin (via R22). AC-coupling the slope compensation ramp is preferred because it avoids adding a DC bias at the CS pin, which would effectively reduce the current limit threshold. Lastly, C21 should be large enough to pass the slope compensation ramp. Making C21 too small results in a transient negative voltage at the CS pin when the RT/CT waveform resets, making very small on-times of the MOSFET impossible. The extra benefit of the slope-compensation signal is to create more noise margin to the leading-edge spike on CS pin from prematurely turning off primary MOSFET.
Figure 9-2 Figure TBD: Current Filtering,
Leading-Edge Blanking, and Slope Compensation