ZHCSK44G December 2009 – November 2022 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Custom Design With WEBENCH? Tools
- 9.2.2.2 Input Bulk Capacitor and Minimum Bulk Voltage
- 9.2.2.3 Transformer Turns Ratio and Maximum Duty CycleG
- 9.2.2.4 Transformer Inductance and Peak Currents
- 9.2.2.5 Output Capacitor
- 9.2.2.6 Current Sensing Network
- 9.2.2.7 Gate Drive Resistor
- 9.2.2.8 VREF Capacitor
- 9.2.2.9 RT/CT
- 9.2.2.10 Start-Up Circuit
- 9.2.2.11 Voltage Feedback Compensation
- 9.2.3 Application Curves
- 9.2.4 Power Supply Recommendations
- 9.2.5 Layout
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- D|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
9.2 Typical Application
A typical application for the UCC28C42-Q1 in an off-line flyback converter is shown in Figure 9-2. The UCC28C42-Q1 uses an inner current control loop that contains a small current sense resistor which senses the primary inductor current ramp. This current sense resistor transforms the inductor current waveform to a voltage signal that is input directly into the primary side PWM comparator. This inner loop determines the response to input voltage changes. An outer voltage control loop involves comparing a portion of the output voltage to a reference voltage at the input of an error amplifier. When used in an off-line isolated application, the voltage feedback of the isolated output is accomplished using a secondary-side error amplifier and adjustable voltage reference, such as the TL431A-Q1 or TL431B-Q1. The error signal crosses the primary to secondary isolation boundary using an opto-isolator whose collector is connected to the VREF pin and the emitter is connected to FB. The outer voltage control loop determines the response to load changes.
Figure 9-2 Typical Application Design
Schematic