东京热一区二区三区,天堂а√中文最新版在线,国产综合久久久久

SLUS829G August 2008 – February 2020 UCC2897A

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RGP|20
- MPQF126G
PW|20
- MPDS362A

散熱焊盤機械數據 (封裝 | 引腳)

RGP|20
- QFND079Y

訂購信息

7.5 Electrical Characteristics

V_DD = 12 V⁽¹⁾, 1-µF capacitor for VDD to GND, 0.01-µF capacitor from VREF to GND, R_ON = R_OFF = 75 kΩ, R_SLOPE = 50 kΩ, –40°C ≤ T_A = T_J ≤ 125°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OVERALL
I_STARTUP	Start-up current	V_DD< V_UVLO		300	500	µA
I_DD	Operating supply current⁽¹⁾⁽²⁾	V_FB = 0 V, V_CS = 0V, Outputs not switching		2	3	mA
HIGH-VOLTAGE BIAS
I_DD-ST	VDD startup current	Current available from VDD during startup, T_A = –40°C to +85°C, V_IN = 36 V⁽³⁾	4	11		mA
I_VIN	JFET leakage current	VIN = 120 V; VDD = 14 V			75	µA
UNDERVOLTAGE LOCKOUT
UVLO	Start threshold voltage		12.2	12.7	13.2	V
	Minimum operating voltage after start		7.6	8	8.4
	Hysteresis		4.4	4.7	5
LINE MONITOR
V_LINEUV	Line UV voltage threshold		1.243	1.268	1.294	V
I_LINEUVHYS	Line UV hysteresis current		–11.5	–13	–14.5	µA
V_LINEOV	Line OV voltage threshold		1.243	1.268	1.294	V
I_LINEOVHYS	Line OV hysteresis current		–11.5	–13	–14.5	µA
Soft-Start
I_SSC	SS charge current	R_ON = 75 kΩ⁽⁴⁾	–10.5	–14.5	–18.5	µA
I_SSD	SS discharge current	R_ON = 75 kΩ⁽⁴⁾	10.5	14.5	18.5	µA
V_SS/SD	Discharge/shutdown threshold voltage		0.4	0.5	0.6	V
VOLTAGE REFERENCE
V_REF	Reference voltage	T_J = 25°C	4.85	5	5.15	V
V_REF	Reference voltage	0 A < I_REF < 5 mA, over temperature	4.75	5	5.25	V
I_SC	Short circuit current	REF = 0 V, T_J = 25°C	–20	–11	–8	mA
INTERNAL SLOPE COMPENSATION
m	Slope	FB = High	–10%	R_CS / R_SLOPE	+10%
OSCILLATOR
f_OSC	Oscillator frequency	T_J = 25°C	237	250	265	kHZ
f_OSC	Oscillator frequency	–40°C < T_J < 125°C; 8.5 V < V_DD < 14.5 V	225		270	kHZ
V_{P_P}	Oscillator amplitude (peak-to-peak)			2		V
SYNCHRONIZATION
	SYNC input high voltage		3			V
	SYNC input low voltage				1.6	V
	SYNC pull down output current			600		µA
	SYNC pull up output current			–600		µA
	SYNC output pulse width			150		ns
t_DEL	SYNC-to-output delay			50		ns
PWM⁽⁵⁾
D_MAX	Maximum duty cycle	R_ON = R_OFF = 75 kΩ, R_DEL = 10 kΩ	66%	70%	74%
	Minimum duty cycle				0%
	PWM offset	CS = 0 V	0.43	0.5	0.61	V
CURRENT SENSE
V_LVL	Current sense level shift voltage		0.4	0.5	0.6	V
V_ERR(max)	Maximum voltage error (clamped)			5
V_CS	Current sense threshold cycle-by-cycle		0.43	0.48	0.53
OUTPUT (OUT AND AUX)
I_OUT(src)	Output source current			–2		A
I_OUT(sink)	Output sink current			2		A
V_OUT(low)	Low-level output voltage	I_OUT = 150 mA		0.4		V
V_OUT(high)	High-level output voltage	I_OUT = –150 mA		11.1		V

(1) Set VDD above the start threshold before setting at 12 V.

(2) Does not include current of the external oscillator network.

(3) The power supply starts with I_DD–ST load on VDD, the part starts up with no load up to 125°C. For more information see the section for VIN and VDD

(4) I_SSC and I_SS/SD are directly proportional to I_RON. See Equation 8.

(5) Maximum pulse width needs to be less than D_MAX, which is a function of RON and R_OFF. For more information on D_MAX, see detailed description for R_OFF in .