| SUPPLY INPUT |
| IRUN |
Supply current, run |
VVDD = 15 V, VVS = 3.9 V, fSW = fSW(max) |
2.3 |
2.9 |
3.4 |
mA |
| IRUNQ |
Quiescent supply current |
VVDD = 15 V, VVS = 3.9 V, fSW = 0 Hz |
1.90 |
2.35 |
2.80 |
mA |
| IWAIT |
Wait supply current |
VVDD= 15 V, VVS = 4.1 V, fSW = fSW(min) |
150 |
270 |
370 |
µA |
| IWAITQ |
Quiescent wait supply current |
VVDD = 15 V, VVS = 4.1 V, fSW = 0 Hz |
150 |
200 |
280 |
µA |
| ISTART |
Supply current before start |
VVDD from 0 V to 5.6 V, VDRAIN = 0 V |
|
65 |
90 |
µA |
| IFAULT |
Supply current after fault |
VVDD = 15 V, fSW = 0 Hz |
|
190 |
260 |
µA |
| UNDER-VOLTAGE LOCKOUT |
| VDDON |
VDD turn-on threshold |
VVDD low to high |
9.0 |
9.5 |
10.0 |
V |
| VDDOFF |
VDD turn-off threshold |
VVDD high to low |
6.0 |
6.5 |
7.0 |
V |
| VDDHV(on) |
HV current source start |
VVDD high to low |
4.8 |
5.2 |
5.6 |
V |
| ΔVUVLO |
UVLO hysteresis |
VDDON – VDDOFF |
2.8 |
3.0 |
3.2 |
V |
| STARTUP CURRENT SOURCE |
| ICH1 |
Startup current with VDD shorted to GND |
VVDD < 250 mV, VDRAIN = 100 V |
–300 |
|
–100 |
µA |
| ICH2 |
Sourced current for startup at high VDD |
VVDD = 8 V, VDRAIN = 100 V |
–9.75 |
|
–0.40 |
mA |
| ICH3 |
Sourced current for startup at low VDD |
VVDD = 2 V, VDRAIN = 100 V |
–13.75 |
|
–1.30 |
mA |
| VS INPUT |
| VVSR |
Regulating level |
Measured in no load condition, TJ = 25°C |
4.01 |
4.05 |
4.09 |
V |
| VVSNC |
Negative clamp level |
IVS = –300 μA, |
–190 |
–250 |
–325 |
mV |
| IVS |
Input bias current |
VVS = 4 V |
–0.25 |
0.00 |
0.25 |
µA |
| PROTECTION |
| IDOCP |
DRAIN over current |
IPK terminal shorted to GND |
0.725 |
0.850 |
0.925 |
A |
| VCSTE_OCP |
Equivalent VCST(OCP) |
VVS = 3.9 V, ID(ocp) x RIPK |
670 |
770 |
830 |
V |
| VCSTE_OCP2 |
Equivalent VCST(OCP2) |
VVS = 3.9 V, ID(ocp2) x RIPK |
|
1200 |
|
V |
| tONMAX(max) |
Maximum FET on time at high load |
VVS < 3.9 V, IPK shorted to GND |
13 |
18 |
24 |
µs |
| tONMAX(min) |
Maximum FET on time at low load |
VVS > 4.1 V, IPK shorted to GND |
4.3 |
6 |
10 |
µs |
| VOVP |
Over-voltage threshold |
At VS input, TJ = 25°C |
4.45 |
4.60 |
4.75 |
V |
| IVSLRUN |
VS line sense run current |
Current out of VS terminal – increasing |
175 |
215 |
260 |
µA |
| IVSLSTOP |
VS line sense stop current |
Current out of VS terminal – decreasing |
60 |
75 |
100 |
µA |
| KVSL |
Line sense IVS ratio |
IVSL(run) / IVSL(stop) |
2.55 |
2.70 |
2.90 |
A/A |
| VDDCLP |
VDD voltage clamp |
IVDDCLP forced = 2 mA |
26 |
28 |
30 |
V |
| IVDDCLP_OC |
VDD clamp over current |
VVDD > 25 V |
4.65 |
6.00 |
7.65 |
mA |
| TJ(stop) |
Thermal shutdown temperature |
Internal junction temperature |
|
150 |
|
°C |
| TJ(hys) |
Thermal shutdown hysteresis |
Internal junction temperature |
|
50 |
|
°C |
| POWER FET |
| BVDSS |
Break-down voltage |
TJ = 25°C |
700 |
|
|
V |
| RDS(on) |
Power FET on resistance |
ID = 150 mA, TJ = 25°C |
|
10.5 |
12.0 |
Ω |
| ID = 150 mA, TJ = 125°C |
|
18.4 |
21.5 |
Ω |
| ILEAKAGE |
DRAIN terminal leakage current |
VDS = 400 V HV, VS = 4.2 V DC TJ = 25°C |
|
|
10 |
µA |
VDS = 400 V HV, VS = 4.2 V DC TJ = 125°C |
|
|
20 |
µA |
VDS = 700 V HV, VS = 4.2 V DC TJ = 25°C |
|
|
10 |
µA |
| CURRENTS |
| ID_PEAK(max) |
Maximum DRAIN peak current |
VVDD = 15 V, IPK terminal shorted to GND, TJ = 25°C |
582 |
600 |
618 |
mA |
| RIPK_SHORT |
IPK to GND resistance Max to assume IPK shorted to GND |
VVDD = 15 V |
|
|
200 |
Ω |
| RIPK(min) |
IPK to GND minimum resistance |
VVDD = 15 V |
900 |
|
|
Ω |
| VCSTE(max) |
Equivalent current sense threshold |
VVDD = 15 V, VVS = 3.9 V, ID_PK(max) × RIPK , TJ = 25°C |
532 |
540 |
548 |
V |
| VCSTE(min) |
Equivalent current sense threshold |
VVDD = 15 V, VVS = 4.1 V, ID_PK(min) × RIPK |
160 |
180 |
200 |
V |
| KAM |
AM control ratio |
VCSE(max) / VCSE(min) |
2.30 |
3.00 |
3.50 |
V/V |
| KCC |
CC regulation gain |
VVDD = 15 V, VVS > 3.9 V; tDEMAG × fSW |
|
0.413 |
|
|
| VCCR |
CC regulation constant |
VVDD = 15 V, VVS < 3.9 V, VCSET(max) × KCC, TJ = 25°C |
216 |
223 |
230 |
V |