ZHCSK45C august 2019 – december 2020 UCC28740-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Revision History
- 6 Revision History
- 7 Pin Configuration and Functions
- 8 Specifications
- 9 Detailed Description
-
10Application and Implementation
- 10.1 Application Information
- 10.2 High Voltage Applications
- 10.3
Typical Application
- 10.3.1 Design Requirements
- 10.3.2
Detailed Design Procedure
- 10.3.2.1 Custom Design With WEBENCH? Tools
- 10.3.2.2 Standby Power Estimate and No-Load Switching Frequency
- 10.3.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
- 10.3.2.4 38
- 10.3.2.5 Transformer Turns-Ratio, Inductance, Primary Peak Current
- 10.3.2.6 Transformer Parameter Verification
- 10.3.2.7 VS Resistor Divider, Line Compensation
- 10.3.2.8 Output Capacitance
- 10.3.2.9 VDD Capacitance, CVDD
- 10.3.2.10 Feedback Network Biasing
- 10.3.3 Application Curves
- 11Power Supply Recommendations
- 12Layout
-
13Device and Documentation Support
- 13.1
Device Support
- 13.1.1 Development Support
- 13.1.2
Device Nomenclature
- 13.1.2.1 Capacitance Terms in Farads
- 13.1.2.2 Duty Cycle Terms
- 13.1.2.3 Frequency Terms in Hertz
- 13.1.2.4 Current Terms in Amperes
- 13.1.2.5 Current and Voltage Scaling Terms
- 13.1.2.6 Transformer Terms
- 13.1.2.7 Power Terms in Watts
- 13.1.2.8 Resistance Terms in Ohms
- 13.1.2.9 Timing Terms in Seconds
- 13.1.2.10 Voltage Terms in Volts
- 13.1.2.11 AC Voltage Terms in VRMS
- 13.1.2.12 Efficiency Terms
- 13.2 Documentation Support
- 13.3 Receiving Notification of Documentation Updates
- 13.4 Community Resources
- 13.5 Trademarks
- 13.1
Device Support
- Mechanical, Packaging, and Orderable Information
10.3.2.6 Transformer Parameter Verification
Because the selected transformer turns-ratio affects the MOSFET VDS and the secondary and auxiliary rectifier reverse voltages, a review of these voltages is important. In addition, internal timing constraints of the UCC28740-Q1 require a minimum on time of the MOSFET (tON) and a minimum demagnetization time (tDM) of the transformer in the high-line minimum-load condition. The selection of fMAX, LP, and RCS affects the minimum tON and tDM.
Equation 19 and Equation 20 determine the reverse voltage stresses on the secondary and auxiliary rectifiers. Stray inductance can impress additional voltage spikes upon these stresses and snubbers may be necessary.
For the MOSFET VDS peak voltage stress, an estimated leakage inductance voltage spike (VLK) is included.
Equation 22 determines if tON(min) exceeds the minimum tON target of 280 ns (maximum tCSLEB). Equation 23 verifies that tDM(min) exceeds the minimum tDM target of 1.2 μs.
