深夜放纵内射少妇,日产国产精品精品a∨,精品香蕉国产一区二区三区四区

ZHCSEK1B December 2013 – October 2015 UCC28722

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DBV|6
- MPDS026Q

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_VDD	Bias supply voltage, VDD			38	V
I_DRV	Continuous base current sink			50	mA
I_DRV	Continuous base current source			Self-limiting	mA
I_VS	Peak current, VS			–1.2	mA
V_DRV	Base drive voltage at DRV		–0.5	Self-limiting	V
	Voltage	VS	–0.75	7	V
	Voltage	CS, CBC	–0.5	5	V
T_J	Operating junction temperature		–55	150	°C
	Lead temperature 0.6 mm from case for 10 seconds			260	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
VDD	Bias supply operating voltage	9	35	V
C_VDD	VDD bypass capacitor	1.0	10	µF
R_CBC	Cable-compensation resistance	10		kΩ
I_VS	VS pin current	−1		mA
T_J	Operating junction temperature	−40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC28722	UNIT
		DBV (SOT-23)
		6 PINS
R_θJA	Junction-to-ambient thermal resistance	180.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	72.2	°C/W
R_θJB	Junction-to-board thermal resistance	44.4	°C/W
ψ_JT	Junction-to-top characterization parameter	5.1	°C/W
ψ_JB	Junction-to-board characterization parameter	43.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	NA	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range, V_VDD = 25 V, HV = open, R_CBC = open, T_A = -40°C to 125°C, T_A = T_J
(unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BIAS SUPPLY INPUT
I_RUN	Supply current, run	I_DRV = 0, run state		2.00	2.65	mA
I_WAIT	Supply current, wait	I_DRV = 0, wait state		95	170	µA
I_START	Supply current, start	I_DRV = 0, V_VDD = 18 V, start state, I_HV = 0		1.0	1.5	µA
I_FAULT	Supply current, fault	I_DRV = 0, fault state		2.00	2.65	mA
UNDERVOLTAGE LOCKOUT
V_VDD(on)	VDD turnon threshold	V_VDD low to high	19	21	23	V
V_VDD(off)	VDD turnoff threshold	V_VDD high to low	7.2	7.7	8.3	V
VS INPUT
V_VSR	Regulating level	Measured at no-load condition, T_J = 25°C⁽¹⁾	3.99	4.05	4.11	V
V_VSNC	Negative clamp level	I_VS = –300 µA, volts below ground	190	250	325	mV
I_VSB	Input bias current	V_VS = 4 V	–0.25	0	0.25	µA
CS INPUT
V_CST(max)	Max CS threshold voltage	V_VS = 3.7 V	730	780	820	mV
V_CST(min)	Min CS threshold voltage	V_VS = 4.35 V	170	190	220	mV
K_AM	AM control ratio	V_CST(max) / V_CST(min)	3.6	4.0	4.4	V/V
V_CCR	Constant current regulating level	CC regulation constant	314	330	347	mV
K_LC	Line compensation current ratio	I_VSLS = –300 µA, I_VSLS / current out of CS pin	24.0	25.0	28.6	A/A
T_CSLEB	Leading-edge blanking time	DRV output duration, V _CS = 1 V	230	290	355	ns
DRIVER
I_DRS(max)	Maximum DRV source current	V_DRV = 2 V, V_VDD = 9 V, V_VS = 3.85 V	31	37	42	mA
I_DRS(min)	Minimum DRV source current	V_DRV = 2 V, V_VDD = 9 V, V_VS = 4.30 V	15	19	23	mA
R_DRVLS	DRV low-side drive resistance	I_DRV = 10 mA		1	2.4	Ω
V_DRCL	DRV clamp voltage	V_VDD = 35 V		5.9	7	V
R_DRVSS	DRV pulldown in start state			20	25	kΩ
TIMING
f_SW(max)	Maximum switching frequency	V_VS = 3.7 V	72	80	89	kHz
f_SW(min)	Minimum switching frequency	V_VS = 4.35 V	570	650	750	Hz
t_ZTO	Zero-crossing timeout delay		2.4	3.1	3.7	µs
PROTECTION
V_OVP	Overvoltage threshold	At VS input, T_J = 25°C⁽¹⁾	4.49	4.60	4.75	V
V_OCP	Overcurrent threshold	At CS input	1.4	1.5	1.6	V
I_VSL(run)	VS line-sense run current	Current out of VS pin increasing	188	225	277	µA
I_VSL(stop)	VS line-sense stop current	Current out of VS pin decreasing	70	80	100	µA
K_VSL	VS line sense ratio	I_VSL(run) / I_VSL(stop)	2.45	2.80	3.05	A/A
T_J(stop)	Thermal shutdown temperature	Internal junction temperature		165		°C
CABLE COMPENSATION
V_CBC(max)	Cable compensation maximum voltage	Voltage at CBC at full load	2.9	3.1	3.5	V
V_CVS(min)	Minimum compensation at VS	V_CBC = open, change in VS regulating level at full load	–55	–15	25	mV
V_CVS(max)	Maximum compensation at VS	V_CBC = 0 V, change in VS regulating level at full load	270	320	385	mV

(1) The regulating level and over voltage at VS decreases with temperature by 0.8 mV/?C. This compensation is included to reduce the power supply output voltage variance over temperature.