ZHCSC62D March 2014 – December 2017 UCC28630 , UCC28631 , UCC28632 , UCC28633 , UCC28634
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 High-Voltage Current Source Start-Up Operation
- 8.3.2 AC Input UVLO / Brownout Protection
- 8.3.3 Active X-Capacitor Discharge (UCC28630 and UCC28633 only)
- 8.3.4 Magnetic Input and Output Voltage Sensing
- 8.3.5 Fixed-Point Magnetic Sense Sampling Error Sources
- 8.3.6 Magnetic Sense Resistor Network Calculations
- 8.3.7 Magnetic Sensing: Power Stage Design Constraints
- 8.3.8 Magnetic Sense Voltage Control Loop
- 8.3.9 Peak Current Mode Control
- 8.3.10 IPEAK Adjust vs. Line
- 8.3.11 Primary-Side Constant-Current Limit (CC Mode)
- 8.3.12 Primary-Side Overload Timer (UCC28630 only)
- 8.3.13 Overload Timer Adjustment (UCC28630 only)
- 8.3.14 CC-Mode IOUT(lim) Adjustment
- 8.3.15 Fault Protections
- 8.3.16 Pin-Fault Detection and Protection
- 8.3.17 Over-Temperature Protection
- 8.3.18 External Fault Input
- 8.3.19 External SD Pin Wake Input (except UCC28633)
- 8.3.20 External Wake Input at VSENSE Pin (UCC28633 Only)
- 8.3.21 Mode Control and Switching Frequency Modulation
- 8.3.22 Frequency Dither For EMI (except UCC28632)
- 8.4 Device Functional Modes
-
9 Applications and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Notebook Adapter, 19.5 V, 65 W
- 9.2.2 UCC28630 Application Schematic
- 9.2.3 Design Requirements
- 9.2.4
Detailed Design Procedure
- 9.2.4.1 Custom Design With WEBENCH? Tools
- 9.2.4.2 Input Bulk Capacitance and Minimum Bulk Voltage
- 9.2.4.3 Transformer Turn Ratio
- 9.2.4.4 Transformer Magnetizing Inductance
- 9.2.4.5 Current Sense Resistor RCS
- 9.2.4.6 Transformer Constraint Verification
- 9.2.4.7 Transformer Selection and Design
- 9.2.4.8 Slope Compensation Verification
- 9.2.4.9 Power MOSFET and Output Rectifier Selection
- 9.2.4.10 Output Capacitor Selection
- 9.2.4.11 Calculation of CC Mode Limit Point
- 9.2.4.12 VDD Capacitor Selection
- 9.2.4.13 Magnetic Sense Resistor Network Selection
- 9.2.4.14 Output LED Pre-Load Resistor Calculation
- 9.2.5 External Wake Pulse Calculation at VSENSE Pin (UCC28633 Only)
- 9.2.6 Energy Star Average Efficiency and Standby Power
- 9.2.7 Application Performance Plots
- 9.3 Dos and Don'ts
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
9.2.4.9 Power MOSFET and Output Rectifier Selection
The initial design target proposed the use of a 100-V Schottky rectifier. The secondary-side reverse voltage stress can be verified using the final transformer design sh own in Equation 52.
The value derived from Equation 52 is close to the original design target of 85 V.
For 65-W load, the average DC output current is 3.35 A for 19.5-V output. However, to reduce losses, a much higher current rated diode is typically used, to yield a much lower forward voltage drop VRECT. As shown in Figure 44, a 30-A rated diode D7 is used in this case, with a forward drop of approximately 0.45 V at 3.5 A, 100°C.
For the primary-side MOSFET, the peak voltage stress can be estimated using Equation 53.
An allowance of at least 100 V must be added to this figure to account for the leakage inductance spike at turn-off. This voltage spike depends on the transformer implementation and the amount of leakage inductance, as well as the specific design of the snubber. A more aggressive snubber may reduce the voltage spike, but at the expense of higher losses in the snubber. A voltage rating of at least 600 V is recommended for the power MOSFET to allow for leakage.
The MOSFET rms current at low line, rated load, can be estimated using Equation 54.
As can be seen in Figure 44, the chosen MOSFET Q1 is a 13-A, 600-V device.