One of the most prominent innovations in the UCC28070A design is the current synthesizer circuitry that synchronously monitors the instantaneous inductor current through a combination of ON-time sampling and OFF-time down-slope emulation.

During the ON-time of the GDA and GDB outputs, the inductor current is recorded at the CSA and CSB pins, respectively, through the current transformer network in each output phase. Meanwhile, the continuous monitoring of the input and output voltages through the VINAC and VSENSE pins permits the UCC28070A to internally recreate the down-slope of the inductor current during the respective OFF-time of each output. Through the selection of the RSYNTH resistor (R_SYN), based on Equation 12, the internal response may be adjusted to accommodate the wide range of inductances expected across the wide array of applications.

During inrush surge events at power up and AC drop-out recovery, V_VSENSE < V_VINAC, the synthesized downslope becomes zero. In this case, the synthesized inductor current remains above the IMO reference and the current loop drives the duty cycle to zero. This avoids excessive stress on the MOSFETs during the surge event. Once V_VINAC falls below V_VSENSE, the duty cycle increases until steady-state operation resumes.

Figure 6-2 Downslope of the Inductor Current

Equation 12.

where:

• L_B = Nominal Zero-Bias Boost Inductance (μH)
• R_S = Sense Resistor (?)
• N_CT = Current-sense Transformer turns ratio
• k_R = R_B / (R_A + R_B) = the resistor-divider attenuation at the VSENSE and VINAC pins