The UCC28070A multiplier generates a reference current which represents the desired wave shape and proportional amplitude of the AC input current. This current is converted to a reference voltage signal by the R_IMO resistor which is scaled in value to match the low-frequency average voltage of the current-sense signals. The instantaneous multiplier current is dependent upon the rectified, scaled input voltage V_VINAC and the voltage-error amplifier output V_VAO. V_VINAC conveys three pieces of information to the multiplier:

• The overall wave-shape of the input voltage (typically sinusoidal).
• The instantaneous input voltage magnitude at any point in the line cycle.
• The rms level of the input voltage (inferred from the peak of the assumed sinusoid).

A major innovation in the UCC28070A multiplier architecture is the internal quantized V_RMS feed-forward (Q_VFF) circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow response to transient line variations. A unique circuit algorithm detects the transition of the peak of V_VINAC through seven thresholds and generates an equivalent VFF level centered within the 8-Q_VFF ranges. The boundaries of the ranges expand with increasing V_IN to maintain an approximately equal-percentage delta between levels. These 8-Q_VFF levels are spaced to accommodate the full universal line range of 85V_RMS to 265V_RMS.

A great benefit of the Q_VFF architecture is that the constant k_VFF factors eliminate any contribution to distortion of the multiplier output, unlike an externally-filtered VINAC signal ripple which unavoidably contains 2nd-harmonic distortion components. Furthermore, the Q_VFF algorithm allows for rapid response to both increasing and decreasing changes in input rms voltage so that disturbances transmitted to the PFC output are minimized. 5% hysteresis in the level thresholds help avoid chattering between Q_VFF levels for V_VINAC voltage peaks near a particular threshold or containing mild ringing or distortion.

The Q_VFF architecture requires that the input voltage be largely sinusoidal, and relies on detecting zero-crossings to adjust Q_VFF downward on decreasing input voltage. Zero-crossings are defined as V_VINAC falling below 0.7V for at least 50μs, typically. For hysteresis in changing levels, falling threshold voltages are 95% of rising threshold voltages.

Table 6-1 shows the relationship between the various V_VINAC peak voltages and the corresponding k_VFF terms for the multiplier equation.

The multiplier output current I_IMO for any line and load condition can thus be determined using Equation 13:

Equation 13.

Because the k_VFF value represents the scaled (V_RMS)² at the center of a level, V_VAO adjusts slightly upwards or downwards when V_VINAC(pk) is either lower or higher than the center of the Q_VFF voltage range to compensate for the difference. This is automatically accomplished by the voltage loop control when V_IN varies, both within a level and after a transition between levels.

The output of the voltage-error amplifier (V_VAO) is clamped at 5V, which represents the maximum PFC output power. This value is used to calculate the maximum reference current at the IMO pin, and sets a limit for the maximum input power allowed (and, as a consequence, limits maximum output power).

Unlike a continuous V_FF situation, where maximum input power is a fixed power at any V_RMS input, the discrete Q_VFF levels permit a variation in maximum input power within limited boundaries as the input V_RMS varies within each level.

The lowest maximum power limit occurs at the V_VINAC voltage of 0.76V, while the highest maximum power limit occurs at the increasing threshold from level-1 to level-2. This pattern repeats at every level transition threshold, considering that decreasing thresholds are 95% of the increasing threshold values. Below V_VINAC = 0.76V, P_IN is always less than P_IN(max), falling linearly to zero with decreasing input voltage.

For example, to design for the lowest maximum power allowable, determine the maximum steady-state (average) output power required of the PFC preregulator and add some additional percentage to account for line drop-out recovery power (to recharge C_OUT while full load power is drawn) such as 10% or 20% of P_OUT(max). Then apply the expected efficiency factor to find the lowest maximum input power allowable:

At the P_IN(max) design threshold, V_VINAC = 0.76V, hence Q_VFF = 0.398 and input V_AC = 73V_RMS (accounting for 2V bridge-rectifier drop) for a nominal 400V output system.

This I_IN(pk) value represents the combined average current through the boost inductors at the peak of the line voltage. Each inductor current is detected and scaled by a current-sense transformer (CT). Assuming equal currents through each interleaved phase, the signal voltage at each current-sense input pin (CSA and CSB) is developed across a sense resistor selected to generate approximately 3V based on ? I_IN(pk) × R_S / N_CT, where R_S is the current-sense resistor and N_CT is the CT turns-ratio.

I_IMO is then calculated at that same lowest maximum-power point, as:

Equation 17.

R_IMO is selected such that:

Therefore:

At the increasing side of the level-1 to level-2 threshold, note that the IMO current would allow higher input currents at low-line:

Equation 20.

However, this current may easily be limited by the programmable peak current limiting (PKLMT) feature of the UCC28070A if required by the power stage design.

The same procedure can be used to find the lowest and highest input power limits at each of the Q_VFF level transition thresholds. At higher line voltages, where the average current with inductor ripple is traditionally below the PKLMT threshold, the full variation of maximum input power is seen, but the input currents are inherently below the maximum acceptable current levels of the power stage.

The performance of the multiplier in the UCC28070A has been significantly enhanced when compared to previous generation PFC controllers, with high linearity and accuracy over most of the input ranges. The accuracy is at its worst as V_VAO approaches 1V because the error of the (V_VAO – 1) subtraction increases and begins to distort the IMO reference current to a greater degree.