ZHCSGJ1 August 2017 UCC27712-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
- 8.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
- 8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
- 8.2.2.4 Selecting Bootstrap Resistor (RBOOT)
- 8.2.2.5 Selecting Gate Resistor RON/ROFF
- 8.2.2.6 Selecting Bootstrap Diode
- 8.2.2.7 Estimate the UCC27712-Q1 Power Losses (PUCC27712-Q1)
- 8.2.2.8 Estimating Junction Temperature
- 8.2.2.9 Operation With IGBT's
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
8.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
The bootstrap capacitor should be sized to have more than enough energy to drive the gate of FET Q1 high, and maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with:
Equation 1. 
This design example targets a boot capacitor ripple voltage of 0.5 V. Therefore, the absolute minimum CBOOT requirement is:
Equation 2. 
In practice, the value of CBOOT needs to be greater than the calculated value. This allows for capacitance shift from DC bias and temperature, and also skipped cycles that occur during load transients. For this design example 2x 220-nF capacitors were chosen for the bootstrap capacitor.
Equation 3. 