ZHCSH10B October 2017 – August 2018 UCC27710
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
- 8.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
- 8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
- 8.2.2.4 Selecting Bootstrap Resistor (RBOOT)
- 8.2.2.5 Selecting Gate Resistor RON/ROFF
- 8.2.2.6 Selecting Bootstrap Diode
- 8.2.2.7 Estimate the UCC27710 Power Losses (PUCC27710)
- 8.2.2.8 Estimating Junction Temperature
- 8.2.2.9 Operation With IGBT's
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
6.6 Dynamic Electrical Characteristics
At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ< +125°C (unless otherwise noted). Currents are positive into and negative out of the specified terminal.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Dynamic Characteristics | ||||||
| tPDLH | Turn-on propagation delay (without deadtime) | LI to LO, HI to HO, HS = COM = 0V | 100 | 140 | 190 | ns |
| tPDHL | Turn-off propagation delay | LI to LO, HI to HO, HS = COM = 0V | 100 | 140 | 190 | |
| tPDRM | Low-to-high delay matching | 8 | 30 | |||
| tPDFM | High-to-low delay matching | 8 | 30 | |||
| tRISE | Turn-on rise time | 10% to 90%, HO/LO with 1000-pF load | 35 | 75 | ||
| tFALL | Turn-off fall time | 10% to 90%, HO/LO with 1000-pF load | 16 | 35 | ||
| tON | Minimum HI/LI ON pulse that changes output state | 0 V to 5 V input signal on HI and LI pins | 40 | 60 | ||
| tOFF | Minimum HI/LI OFF pulse that changes output state | 5 V to 0 V input signal on HI and LI pins | 40 | 75 | ||
| DT | Deadtime | Internal Deadtime for Interlock | 95 | 150 | 200 | |
Figure 1. Typical Test Timing Diagram