Table 1. UCC27528-Q1 Features and Benefits

8.3.1 V_DD and Undervoltage Lockout

The UCC27528-Q1 device has internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply-circuit blocks. When the VDD supply is rising and the level is still below UVLO threshold, the circuit (as shown in the Functional Block Diagram) holds the output low, regardless of the status of the inputs. The UVLO threshold is 4.25 V (typical) with 350-mV hysteresis (typical). This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also when droops in the VDD bias voltage occur when the system commences switching and a sudden increase in the I_DD current occurs. The ability to operate at low-voltage levels, such as below 5 V, along with best-in-class switching characteristics, is well suited for driving emerging GaN-power semiconductor devices.

For example, at power-up, the UCC27528-Q1 driver device output remains low until the V_DD voltage reaches the UVLO threshold if the enable pin is active or floating. The magnitude of the OUT signal rises with V_DD until steady-state V_DD is reached. The non-inverting operation in Figure 20 shows that the output remains low until the UVLO threshold is reached. The output is then in-phase with the input.

Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface-mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to the VDD to GND pins of the gate-driver device. In addition, to help deliver the high-current peaks required by the load, a larger capacitor (such as a 1-μF capacitor) with relatively low ESR should be connected in parallel and close proximity. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels and switching frequencies in the application.

Figure 20. Power-Up Non-Inverting Driver

8.3.2 Operating Supply Current

The UCC27528-Q1 device features very low quiescent I_DD currents. Figure 3, Figure 4, and Figure 5 list the typical operating supply current in the UVLO state and fully-on state (under static and switching conditions). The I_DD current that is present when the device is fully on and the outputs are in a static state (DC high or DC low, see Figure 4) represents lowest quiescent I_DD current when all the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent I_DD current, the average I_OUT current from switching, and any current related to pullup resistors on the enable pins and inverting input pins.

Figure 15 shows a complete characterization of the I_DD current as a function of switching frequency at different V_DD bias voltages under 1.8-nF switching load in both channels. The strikingly linear variation and close correlation with the theoretical value of the average I_OUT indicates negligible shoot-through inside the gate-driver device attesting to the high-speed characteristics.

8.3.3 Input Stage

The input pins of UCC27528-Q1 gate driver device are based on CMOS input threshold logic. In CMOS input threshold logic the threshold voltage level is a function of the bias voltage on the VDD pin of the device. The typical high threshold is 55% of the VDD supply voltage and the typical low threshold is 38% of the VDD supply voltage. Built-in hysteresis is available which is typically 17% of the VDD supply voltage.

In most applications, the absolute value of the threshold voltage offered by the CMOS logic is higher (for example, V_{IN_H} = 5.5 V if V_DD = 10 V) than what is offered by the more common TTL and CMOS-compatible input threshold logic where V_{IN_H} is typically less than 3 V. The same is true of the input-threshold hysteresis parameter as well. This feature offers the following benefits:

• Better noise immunity which is desirable in high power systems.
• Ability to accept slow dV/dt input signals, which allows designers to use RCD circuits on the input pin to program propagation delays in the application, as shown in Figure 21.

Figure 21. Using RCD Circuits

Equation 1.

The UCC27528-Q1 device features an important feature, whenever any of the input pins is in a floating condition, the output of the respective channel is held in the low state. Holding the respective channel in the low state is achieved by using GND pulldown resistors on all the non-inverting input pins (INA, INB), as shown in the Functional Block Diagram.

• To drive channel x (x = A or B) in a non-inverting configuration, apply the PWM control input signal to one of the IN pins. In this case, the unused IN pin must be biased low (for example, tied to GND) to enable the output of this channel.
  • Alternately, the unused IN pin can be used to implement the enable and disable function using an external logic signal. The output pin is disabled when the unused IN pin is biased high and the OUT pin is enabled when the unused IN pin is biased low.

See Table 2 and Figure 24 for additional clarification.

8.3.4 Enable Function

The enable function is an extremely beneficial feature in gate driver devices, especially for certain applications such as synchronous rectification where the driver outputs can be disabled in light-load conditions to prevent negative current circulation and to improve light-load efficiency.

The UCC27528-Q1 device has independent enable pins, ENx, for exclusive control of the operation of each driver channel. The enable pins are based on a non-inverting configuration (active-high operation). Therefore, when the ENx pins are driven high the drivers are enabled and when ENx pins are driven low and the drivers are disabled. Similar to the input pins, the enable pins are also based on a TTL and CMOS-compatible input threshold logic that is independent of the supply voltage and can be effectively controlled using logic signals from 3.3-V and 5-V microcontrollers. The UCC27528-Q1 device also features tight control of the enable-function threshold voltage levels which eases system design considerations and ensures stable operation across temperature (see Figure 8). The ENx pins are internally pulled up to the VDD supply using pullup resistors as a result of which the outputs of the device are enabled in the default state. Therefore, the ENx pins can be left floating or not connected (NC) for standard operation in which case the enable feature is not needed. This ability allows the UCC27528-Q1 device to be pin-to-pin compatible with TI’s previous-generation drivers, the UCC27323, UCC273234, and UCC273235 device, where pin 1 and pin 8 are NC pins. If the Channel A and Channel B inputs and outputs are connected in parallel to increase the driver current capacity, the ENA and ENB pins should be connected and driven together.

8.3.5 Output Stage

The UCC27528-Q1 output stage features a unique architecture on the pullup structure which delivers the highest-peak source current when it is most needed during the Miller plateau region of the power-switch turn-on transition (when the power switch drain and collector voltage experiences dV/dt). The output-stage pullup structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The N-Channel MOSFET provides a brief boost in the peak sourcing current which enables fast turn-on. This boost is accomplished by briefly turning on the N-Channel MOSFET during a short time frame when the output is changing state from low to high.

Figure 22. UCC27528-Q1 Gate Driver Output Structure

The R_OH parameter (see the Electrical Characteristics table) is a DC measurement and is representative of the on-resistance of the P-Channel device only because the N-Channel device is held in the off state in DC condition and is turned on only for a short time frame when the output changes state from low to high. Therefore, the effective resistance of UCC27528-Q1 pullup stage during turn-on instant is much lower than what is represented by R_OH parameter.

The pulldown structure in the UCC27528-Q1 device is simply composed of a N-Channel MOSFET. The R_OL parameter (see the Electrical Characteristics table), which is also a DC measurement, is representative of the impedance of the pulldown stage in the device. In the UCC27528-Q1 device, the effective resistance of the hybrid pullup structure during turnon is estimated on design considerations as approximately 1.5 × R_OL.

Each output stage in the UCC27528-Q1 device is capable of supplying 5-A peak source and 5-A peak sink current pulses. The output voltage swings between VDD and GND, providing rail-to-rail operation because of the MOS output stage which delivers very-low dropout. The presence of the MOSFET body diodes also offers low impedance to switching overshoots and undershoots which means that in many cases, external Schottky diode clamps can be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction.

The UCC27528-Q1 device is particularly suited for dual-polarity, symmetrical drive-gate transformer applications where the primary winding of transformer driven by the OUTA and OUTB pins, with the inputs INA and INB driven complementary to each other. The device is well suited for these applications because of the extremely low dropout offered by the MOS output stage of the device, both during high (V_OH) and low (V_OL) states along with the low impedance of the driver output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance. The low propagation delays also ensure accurate reset for high-frequency applications.

For applications that have zero voltage switching during power MOSFET turn-on or turn-off interval, the driver supplies high-peak current for fast switching even though the miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before power MOSFET is switched on.

8.3.6 Low Propagation Delays and Tightly Matched Outputs

The UCC27528-Q1 driver devices offer a very low propagation delay of 17-ns (typical) between input and output which offers lowest level of pulse transmission distortion available in the industry for high-frequency switching applications. For example in synchronous rectifier applications, the SR MOSFETs can be driven with very low distortion when a single driver device is used to drive both the SR MOSFETs. Further, the driver devices also feature an extremely accurate, 1-ns (typ) matched internal propagation delays between the two channels which is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC application, a pair of paralleled MOSFETs may be driven independently using each output channel, which the inputs of both channels are driven by a common control signal from the PFC controller device. In this case the 1-ns delay matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum of turn-on delay difference.

Since the CMOS input threshold of UCC27528-Q1 allows the use of slow dV/dt input signals, when paralleling outputs for obtaining higher peak output current capability, it is recommended to connect external gate resistors directly to the output pins to avoid shoot-through current conduction between the 2 channels, as shown in Figure 23. While the two channels are inherently very well matched (4-ns Max propagation delay), it should be noted that there may be differences in the input threshold voltage level between the two channels or differences in the input signals which can cause the delay between the two outputs.

Figure 23. Slow Input Signal May Cause Shoot-Through Between Channels During Paralleling

Table 2. Device Logic Table