ZHCSLM8B August 2020 – February 2024 UCC21759-Q1
PRODUCTION DATA
UCC21759-Q1DW SOIC (16)Top View| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AIN | 1 | I | Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. If not used, short to COM |
| DESAT | 2 | I | Desaturation current protection input. If not used, short to COM |
| COM | 3 | P | Common ground reference, connecting to emitter pin for IGBT or source pin for SiC-MOSFET |
| OUTH | 4 | O | Gate driver output pull up |
| VDD | 5 | P | Positive supply rail for gate drive voltage, Bypassing a >10μF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin. |
| OUTL | 6 | O | Gate driver output pull down |
| CLMPI | 7 | O | Internal active Miller clamp, connecting this pin directly to the gate of the power transistor. If not used, short to VEE |
| VEE | 8 | P | Negative supply rail for gate drive voltage. Bypassing a >10μF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin. |
| GND | 9 | P | Input power supply and logic ground reference |
| IN+ | 10 | I | Non-inverting gate driver control input. Tie to VCC if unused. |
| IN– | 11 | I | Inverting gate driver control input. If not used, short to GND |
| RDY | 12 | O | Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other RDY signals |
| FLT | 13 | O | Active low fault alarm output upon over current or short circuit detection. FLT is in open drain configuration and can be paralleled with other faults |
| RST/EN | 14 | I | The RST/EN serves two purposes: 1) Enable / shutdown of the output side. The FET is turned off by a regular turn-off, if terminal EN is set to low; 2) Resets the DESAT condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns. A reset of signal FLT is asserted at the rising edge of terminal RST/EN. For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to low. |
| VCC | 15 | P | Input power supply from 3V to 5.5V, bypassing a >1μF capacitor to GND. Place decoupling capacitor close to the pin. |
| APWM | 16 | O | Isolated analog sensing PWM output. If not used, leave floating or tie a parallel capacitor to GND |