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ZHCSFM4B september 2016 – december 2021 UCC21521

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DW|16
- MSOI003I

散熱焊盤機械數據 (封裝 | 引腳)

DW|16
- QFND505A

訂購信息

6.9 Electrical Characteristics

V_VCCI = 3.3 V or 5 V, 0.1-μF capacitor from VCCI to GND, V_VDDA = V_VDDB = 12 V or 15 V⁽¹⁾, 1-μF capacitor from VDDA and VDDB to VSSA and VSSB, T_A = –40°C to +125°C, (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_VCCI	VCCI quiescent current	V_INA = 0 V, V_INB = 0 V		1.5	2.0	mA
I_VDDA, I_VDDB	VDDA and VDDB quiescent current	V_INA = 0 V, V_INB = 0 V		1.0	1.8	mA
I_VCCI	VCCI per channel operating current	(f = 500 kHz) current per channel, C_OUT = 100 pF		2.0		mA
I_VDDA, I_VDDB	VDDA and VDDB operating current	(f = 500 kHz) current per channel, C_OUT = 100 pF, VDD=12 V		2.5		mA
I_VDDA, I_VDDB	VDDA and VDDB operating current	(f = 500 kHz) current per channel, C_OUT = 100 pF, VDD=15 V		3.0		mA
VCCI UVLO THRESHOLDS
V_{VCCI_ON}	Rising threshold		2.55	2.7	2.85	V
V_{VCCI_OFF}	Falling threshold VCCI_OFF		2.35	2.5	2.65	V
V_{VCCI_HYS}	Threshold hysteresis			0.2		V
UCC21521ADW VDD UVLO THRESHOLDS (5-V UVLO VERSION)
V_{VDDA_ON}, V_{VDDB_ON}	Rising threshold VDDA_ON, VDDB_ON		5.2	5.8	6.3	V
V_{VDDA_OFF}, V_{VDDB_OFF}	Falling threshold VDDA_OFF, VDDB_OFF		4.9	5.5	6	V
V_{VDDA_HYS}, V_{VDDB_HYS}	Threshold hysteresis			0.3		V
UCC21521DW VDD UVLO THRESHOLDS (8-V UVLO VERSION)
V_{VDDA_ON,} V_{VDDB_ON}	Rising threshold VDDA_ON, VDDB_ON		8	8.5	9	V
V_{VDDA_OFF,} V_{VDDB_OFF}	Falling threshold VDDA_OFF, VDDB_OFF		7.5	8	8.5	V
V_{VDDA_HYS,} V_{VDDB_HYS}	Threshold hysteresis			0.5		V
UCC21521CDW VDD UVLO THRESHOLDS (12-V UVLO VERSION)
V_{VDDA_ON}, V_{VDDB_ON}	Rising threshold VDDA_ON, VDDB_ON		12.5	13.5	14.5	V
V_{VDDA_OFF,} V_{VDDB_OFF}	Falling threshold VDDA_OFF, VDDB_OFF		11.5	12.5	13.5	V
V_{VDDA_HYS,} V_{VDDB_HYS}	Threshold hysteresis			1.0		V
INA and INB
V_INAH, V_INBH	Input high voltage		1.6	1.8	2	V
V_INAL, V_INBL	Input low voltage		0.8	1	1.2	V
V_{INA_HYS}, V_{INB_HYS}	Input hysteresis			0.8		V
V_INA, V_INB	Negative transient, ref to GND, 50 ns pulse	Not production tested, bench test only	–5			V
EN THRESHOLDS
V_ENH	Enable high voltage		2.0			V
V_ENL	Enable low voltage				0.8	V
OUTPUT
I_OA+, I_OB+	Peak output source current	C_VDD = 10 μF, C_LOAD = 0.18 μF, f = 1 kHz, bench measurement		4		A
I_OA-, I_OB-	Peak output sink current	C_VDD = 10 μF, C_LOAD = 0.18 μF, f = 1 kHz, bench measurement		6		A
R_OHA, R_OHB	Output resistance at high state	I_OUT = –10 mA, T_A = 25°C, R_OHA, R_OHBdo not represent drive pull-up performance. See t_RISE in Switching Characteristics and Output Stage for details.		5		Ω
R_OLA, R_OLB	Output resistance at low state	I_OUT = 10 mA, T_A = 25°C		0.55		Ω
V_OHA, V_OHB	Output voltage at high state	V_VDDA, V_VDDB = 12 V, I_OUT = –10 mA, T_A = 25°C		11.95		V
V_OLA, V_OLB	Output voltage at low state	V_VDDA, V_VDDB = 12 V, I_OUT = 10 mA, T_A = 25°C		5.5		mV
DEADTIME AND OVERLAP PROGRAMMING
Dead time		Pull DT pin to VCCI	Overlap determined by INA INB			-
		DT pin is left open, min spec characterized only, tested for outliers	0	8	15	ns
		R_DT = 20 kΩ	160	200	240	ns

(1) VDDA=VDDB=12 V is used for the test condition of 5-V and 8-V UVLO, and VDDA=VDDB = 15 V is used for 12-V UVLO.