ZHCSH68G November 2017 – November 2024 UCC21220 , UCC21220A
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Designing INA/INB Input Filter
- 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
- 9.2.2.3 Gate Driver Output Resistor
- 9.2.2.4 Estimating Gate Driver Power Loss
- 9.2.2.5 Estimating Junction Temperature
- 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
- 9.2.2.7 Application Circuits with Output Stage Negative Bias
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Revision History
- 14Mechanical, Packaging, and Orderable Information
9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with Equation 18:
where
- QG: Gate charge of the power transistor.
- IVDD: The channel self-current consumption with no load at 100kHz.
Therefore, the absolute minimum CBoot requirement is:
where
- ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.
In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients. Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the VDD and VSS pins as possible. A 50-V 1-μF capacitor is chosen in this example.
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during initial CBOOT charging cycles, the bootstrap diode has highest reverse recovery current and losses.