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ZHCSKL1A December 2019 – May 2022 TUSS4440

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RTJ|20
- MPQF156F

散熱焊盤機械數據 (封裝 | 引腳)

RTJ|20
- QFND016S

訂購信息

6.7 Receiver Characteristics

over operating free-air temperature range, V_VPWR, V_VDRV and V_VDD recommended voltage range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
G_LNA	Low-noise amplifier fixed gain	LNA_GAIN = 0x00; f_{DRV_CLK}= 58 KHz	13.7	15	16.8	V/V
G_LNA		LNA_GAIN = 0x01; f_{DRV_CLK}= 58 KHz	9.4	10	12
G_LNA		LNA_GAIN = 0x10; f_{DRV_CLK}= 58 KHz	17.6	20	21.8
G_LNA		LNA_GAIN = 0x11; f_{DRV_CLK}= 58 KHz	11.6	12.5	14.2
DR_{VIN_MIN}	Minimum receive input⁽²⁾	LOGAMP_DIS_FIRST=0x0;LOGAMP_DIS_LAST=0x0 LNA_GAIN=0x00; ERR_LOG < ± 3dB; f_{DRV_CLK} < 500KHz		2.4		μVrms
DR_{VIN_MAX}	Maximum receive input⁽²⁾			48		mVrms
SL_AFE	Slope of analog front end⁽⁴⁾	VOUT_SCALE_SEL = 0x0; f_{DRV_CLK}= 58 KHz	25	29.7	33	mV/dB
SL_AFE	Slope of analog front end⁽⁴⁾	VOUT_SCALE_SEL = 0x1; f_{DRV_CLK}= 58 KHz	38	45.1	46	mV/dB
DR_AFE	Receiver path dynamic range (minimum to maximum input)⁽²⁾	LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0 ERR_LOG < ± 3 dB; f_{DRV_CLK} < 500 KHz	82		92	dB
		LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x1 ERR_LOG < ± 3 dB; f_{DRV_CLK} < 500 KHz	74		86
		LOGAMP_DIS_FIRST = 0x1; LOGAMP_DIS_LAST=0x1 ERR_LOG < ± 3dB; f_{DRV_CLK} < 500 KHz	59		70
	Receiver path dynamic Range (noise floor to maximum input)⁽³⁾	LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0 ERR_LOG < ± 3 dB; f_{DRV_CLK} < 500 KHz	74		84
BW_LOG	Logamp bandwidth	Information only	40		1000	KHz
INT_LOG	Intercept point in dBV	LOGAMP_DIS_FIRST=0x0; LOGAMP_DIS_LAST=0x0; f_{DRV_CLK}= 40 KHz	-108		-97	dBV
		LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST=0x1; f_{DRV_CLK}= 40 KHz	-94		-86
		LOGAMP_DIS_FIRST = 0x1; LOGAMP_DIS_LAST=0x1; f_{DRV_CLK}= 40 KHz	-80		-70
ERR_LOG	Log conformance error	Information only	-3		3	dB
f_BPF	Configurable range of center frequency of BPF	BPF_BYPASS = 0x0; BPF_FC_TRIM = 0x0; set by different values of BPF_HPF_FREQ	40		500	KHz
Q_BPF	Q of bandpass filter	BPF_BYPASS = 0x0; BPF_Q_SEL = 0x0⁽¹⁾	3	4	5.2
R_LPF	Internal resistor on FLT pin to ground			6.25		K?
V_{O_PDSTL}	Output pedestal level⁽²⁾	V_VDD= 3.3 V; f_{DRV_CLK} = 40 KHz; VOUT_SCALE_SEL = 0x0 LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0	0.3		0.45	V
V_{O_PDSTL}	Output pedestal level⁽²⁾	V_VDD= 5.0 V; f_{DRV_CLK} = 40 KHz; VOUT_SCALE_SEL = 0x1 LOGAMP_DIS_FIRST = 0x0;LOGAMP_DIS_LAST = 0x0	0.45		0.675	V
V_{N_pk_pk}	Output peak-to-peak noise	V_VDD=3.3 V; f_{DRV_CLK} = 40 KHz; C_FLT = 15 nF; VOUT_SCALE_SEL = 0x0 LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST=0x0	50		200	mVpp
V_{N_pk_pk}	Output peak-to-peak noise	V_VDD=5.0 V; f_{DRV_CLK} = 40 KHz; C_FLT = 15 nF; VOUT_SCALE_SEL = 0x1 LOGAMP_DIS_FIRST = 0x0; LOGAMP_DIS_LAST = 0x0	75		300	mVpp

(1) Other choices of Q possible.

(2) Measured with effectively very large C_FLT. Actual minimum signal detectable will depend on V_{N_pk_pk}. Minimum and maximum input levels are defined by ERR_LOG.

(3) Measured with different C_FLT values according to Equation 3. Noise floor is set by V_{N_PK_PK} in addition to V_{O_PDSTL}.

(4) Slope measured with factory trim at f_{DRV_CLK}= 58 KHz. Slope can be adjusted with LOGAMP_SLOPE_ADJ bits for different f_{DRV_CLK} settings.