ZHCSJZ1 June 2019 TUSB8043A
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5
Register Maps
- 8.5.1 Configuration Registers
- 8.5.2 ROM Signature Register
- 8.5.3 Vendor ID LSB Register
- 8.5.4 Vendor ID MSB Register
- 8.5.5 Product ID LSB Register
- 8.5.6 Product ID MSB Register
- 8.5.7 Device Configuration Register
- 8.5.8 Battery Charging Support Register
- 8.5.9 Device Removable Configuration Register
- 8.5.10 Port Used Configuration Register
- 8.5.11 Device Configuration Register 2
- 8.5.12 USB 2.0 Port Polarity Control Register
- 8.5.13 UUID Registers
- 8.5.14 Language ID LSB Register
- 8.5.15 Language ID MSB Register
- 8.5.16 Serial Number String Length Register
- 8.5.17 Manufacturer String Length Register
- 8.5.18 Product String Length Register
- 8.5.19 Device Configuration Register 3
- 8.5.20 USB 2.0 Only Port Register
- 8.5.21 Serial Number String Registers
- 8.5.22 Manufacturer String Registers
- 8.5.23 Product String Registers
- 8.5.24 Additional Feature Configuration Register
- 8.5.25 SMBus Device Status and Command Register
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
Discrete USB Hub Product
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Upstream Port Implementation
- 9.2.1.2.2 Downstream Port 1 Implementation
- 9.2.1.2.3 Downstream Port 2 Implementation
- 9.2.1.2.4 Downstream Port 3 Implementation
- 9.2.1.2.5 Downstream Port 4 Implementation
- 9.2.1.2.6 VBUS Power Switch Implementation
- 9.2.1.2.7 Clock, Reset, and Misc
- 9.2.1.2.8 TUSB8043A Power Implementation
- 9.2.1.3 Application Curves
- 9.2.1
Discrete USB Hub Product
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RGC|64
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGC|64
訂購信息
8.3.5 Clock Generation
The TUSB8043A accepts a crystal input to drive an internal oscillator or an external clock source. If a clock is provided to XI instead of a crystal, XO is left open. Otherwise, if a crystal is used, the connection needs to follow the guidelines below. Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as possible and away from any switching leads. It is also recommended to minimize the capacitance between XI and XO. This can be accomplished by shielding C1 and C2 with the clean ground lines.
Figure 2. TUSB8043A Clock