ZHCSJZ1 June 2019 TUSB8043A
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5
Register Maps
- 8.5.1 Configuration Registers
- 8.5.2 ROM Signature Register
- 8.5.3 Vendor ID LSB Register
- 8.5.4 Vendor ID MSB Register
- 8.5.5 Product ID LSB Register
- 8.5.6 Product ID MSB Register
- 8.5.7 Device Configuration Register
- 8.5.8 Battery Charging Support Register
- 8.5.9 Device Removable Configuration Register
- 8.5.10 Port Used Configuration Register
- 8.5.11 Device Configuration Register 2
- 8.5.12 USB 2.0 Port Polarity Control Register
- 8.5.13 UUID Registers
- 8.5.14 Language ID LSB Register
- 8.5.15 Language ID MSB Register
- 8.5.16 Serial Number String Length Register
- 8.5.17 Manufacturer String Length Register
- 8.5.18 Product String Length Register
- 8.5.19 Device Configuration Register 3
- 8.5.20 USB 2.0 Only Port Register
- 8.5.21 Serial Number String Registers
- 8.5.22 Manufacturer String Registers
- 8.5.23 Product String Registers
- 8.5.24 Additional Feature Configuration Register
- 8.5.25 SMBus Device Status and Command Register
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
Discrete USB Hub Product
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Upstream Port Implementation
- 9.2.1.2.2 Downstream Port 1 Implementation
- 9.2.1.2.3 Downstream Port 2 Implementation
- 9.2.1.2.4 Downstream Port 3 Implementation
- 9.2.1.2.5 Downstream Port 4 Implementation
- 9.2.1.2.6 VBUS Power Switch Implementation
- 9.2.1.2.7 Clock, Reset, and Misc
- 9.2.1.2.8 TUSB8043A Power Implementation
- 9.2.1.3 Application Curves
- 9.2.1
Discrete USB Hub Product
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
7.6 Timing Requirements
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| Power-on timings. Refer to Figure 1 | |||||
| td1 | VDD stable before VDD33 stable. (2) (3) | 0 | ms | ||
| td2 | VDD and VDD33 before de-assertion of GRSTz. | 3 | ms | ||
| tsu_io | Setup for MISC inputs. (1) | 0.1 | µs | ||
| thd_io | Hold for MISC inputs. (1) | 0.1 | µs | ||
| tVDD33_RAMP | VDD33 supply ramp requirement. | 0.2 | 100 | ms | |
| tVDD_RAMP | VDD supply ramp requirement. | 0.2 | 100 | ms | |
(1) MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL.
(2) As long as GRSTz is de-asserted after both supplies are stable, there is no power-on relationship between VDD33 and VDD. If GRSTz is only connected to a capacitor to GND, then VDD must be stable minimum of 10 µs before VDD33.
(3) An active reset is required if the VDD33 supply is stable before VDD supply. This active reset shall meet the 3 ms power-up delay counting from both power supplies stable to de-assertion of GRSTz.
Figure 1. Power-Up Timing Requirements